From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753980AbdDJNXb (ORCPT ); Mon, 10 Apr 2017 09:23:31 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:55303 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753841AbdDJNTG (ORCPT ); Mon, 10 Apr 2017 09:19:06 -0400 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC Date: Mon, 10 Apr 2017 18:47:57 +0530 Message-ID: <20170410131823.26485-7-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Icenowy Zheng The config structure of H3 in phy-sun4i-usb driver have the PHYCTL register offset missing. Add it. From the BSP source code, we know that the offset should be 0x10. Signed-off-by: Icenowy Zheng Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-sun4i-usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c index 62b4d25448c6..a650f283f6ff 100644 --- a/drivers/phy/phy-sun4i-usb.c +++ b/drivers/phy/phy-sun4i-usb.c @@ -821,6 +821,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .num_phys = 4, .type = sun8i_h3_phy, .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, .dedicated_clocks = true, .enable_pmu_unk1 = true, }; -- 2.11.0