From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754030AbdDKIT0 (ORCPT ); Tue, 11 Apr 2017 04:19:26 -0400 Received: from bombadil.infradead.org ([65.50.211.133]:53038 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752537AbdDKISj (ORCPT ); Tue, 11 Apr 2017 04:18:39 -0400 Date: Tue, 11 Apr 2017 10:18:30 +0200 From: Peter Zijlstra To: Jin Yao Cc: acme@kernel.org, jolsa@kernel.org, mingo@redhat.com, alexander.shishkin@linux.intel.com, Linux-kernel@vger.kernel.org, ak@linux.intel.com, kan.liang@intel.com, yao.jin@intel.com, linuxppc-dev@lists.ozlabs.org, Thomas Gleixner Subject: Re: [PATCH v3 2/5] perf/x86/intel: Record branch type Message-ID: <20170411081830.57372og2mzkhiftr@hirez.programming.kicks-ass.net> References: <1491908193-25418-1-git-send-email-yao.jin@linux.intel.com> <1491908193-25418-3-git-send-email-yao.jin@linux.intel.com> <20170411075219.bcteozodfkmwo45f@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170411075219.bcteozodfkmwo45f@hirez.programming.kicks-ass.net> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 11, 2017 at 09:52:19AM +0200, Peter Zijlstra wrote: > On Tue, Apr 11, 2017 at 06:56:30PM +0800, Jin Yao wrote: > > @@ -960,6 +1006,11 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) > > cpuc->lbr_entries[i].from = 0; > > compress = true; > > } > > + > > + if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE) > > + cpuc->lbr_entries[i].type = common_branch_type(type); > > + else > > + cpuc->lbr_entries[i].type = PERF_BR_NONE; > > } I was wondering WTH you did that else; because it should already be 0 (aka, BR_NONE). Then I found intel_pmu_lbr_read_32() is already broken, and you just broke intel_pmu_lbr_read_64(). Arguably we should add a union on the last __u64 with a name for the entire thing, but the below is the minimal fix. --- Subject: perf,x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32() From: Peter Zijlstra Date: Tue Apr 11 10:10:28 CEST 2017 When the perf_branch_entry::{in_tx,abort,cycles} fields were added, intel_pmu_lbr_read_32() wasn't updated to initialize them. Fixes: 135c5612c460 ("perf/x86/intel: Support Haswell/v4 LBR format") Signed-off-by: Peter Zijlstra (Intel) --- --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -507,6 +507,9 @@ static void intel_pmu_lbr_read_32(struct cpuc->lbr_entries[i].to = msr_lastbranch.to; cpuc->lbr_entries[i].mispred = 0; cpuc->lbr_entries[i].predicted = 0; + cpuc->lbr_entries[i].in_tx = 0; + cpuc->lbr_entries[i].abort = 0; + cpuc->lbr_entries[i].cycles = 0; cpuc->lbr_entries[i].reserved = 0; } cpuc->lbr_stack.nr = i;