From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932069AbdDMULK (ORCPT ); Thu, 13 Apr 2017 16:11:10 -0400 Received: from mail.skyhub.de ([5.9.137.197]:40946 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755416AbdDMULI (ORCPT ); Thu, 13 Apr 2017 16:11:08 -0400 From: Borislav Petkov To: X86 ML Cc: LKML , Tony Luck , linux-edac Subject: [PATCH] x86/mce: Enable PPIN for Knights Landing/Mill Date: Thu, 13 Apr 2017 22:10:56 +0200 Message-Id: <20170413201056.10525-1-bp@alien8.de> X-Mailer: git-send-email 2.11.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Piotr Luc Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so add their CPUIDs to the whitelist of supported processors. Signed-off-by: Piotr Luc Cc: Tony Luck Cc: linux-edac Cc: x86-ml Link: http://lkml.kernel.org/r/20170408172004.8463-1-piotr.luc@intel.com Signed-off-by: Borislav Petkov --- arch/x86/kernel/cpu/mcheck/mce_intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index 190b3e6cef4d..e84db79ef272 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -481,6 +481,9 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_XEON_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_XEON_PHI_KNL: + case INTEL_FAM6_XEON_PHI_KNM: + if (rdmsrl_safe(MSR_PPIN_CTL, &val)) return; -- 2.11.0