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From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: alcooperx@gmail.com, opendmb@gmail.com,
	Florian Fainelli <f.fainelli@gmail.com>,
	Will Deacon <will.deacon@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	linux-kernel@vger.kernel.org (open list:PERFORMANCE EVENTS
	SUBSYSTEM)
Subject: [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53
Date: Thu, 20 Apr 2017 12:05:43 -0700	[thread overview]
Message-ID: <20170420190546.7453-1-f.fainelli@gmail.com> (raw)

Hi,

While investigating why there were no L2 cache events generated for a Cortex
A53-like PMU, it turned out that none of the L2 cache events were mapped.

This is also the case for ARMv8 PMUv3, which seems a little odd considering
they are defined.

Thanks!

Florian Fainelli (2):
  arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills
  arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3

 arch/arm64/kernel/perf_event.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

-- 
2.9.3

             reply	other threads:[~2017-04-20 19:05 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-20 19:05 Florian Fainelli [this message]
2017-04-20 19:05 ` [PATCH 1/2] arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills Florian Fainelli
2017-04-20 19:05 ` [PATCH 1/2] arm64: pmu: " Florian Fainelli
2017-04-20 19:05 ` [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli
2017-04-25 12:44   ` Will Deacon
2017-04-25 17:13     ` Florian Fainelli
2017-04-27 17:36       ` Will Deacon
2017-04-28 14:15         ` Catalin Marinas
2017-04-28 14:17           ` Will Deacon

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