From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
<linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] clk: tegra: fix SS control on PLL enable/disable
Date: Thu, 4 May 2017 10:42:26 +0300 [thread overview]
Message-ID: <20170504074226.GR30730@tbergstrom-lnx.Nvidia.com> (raw)
In-Reply-To: <20170422023848.GJ7065@codeaurora.org>
On Fri, Apr 21, 2017 at 07:38:48PM -0700, Stephen Boyd wrote:
> On 04/20, Peter De Schrijver wrote:
> > PLL SS was only controlled when setting the PLL rate, not when the PLL
> > itself is enabled or disabled. This means that if the PLL rate was set
> > before the PLL is enabled, SS will not be enabled, even when configured.
> >
> > Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
>
> Fixes tag? Or this isn't a problem right now, just future fix?
>
This isn't a problem right now, at least noone complained about it.
Peter.
next prev parent reply other threads:[~2017-05-04 7:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-20 12:39 Peter De Schrijver
2017-04-22 2:38 ` Stephen Boyd
2017-05-04 7:42 ` Peter De Schrijver [this message]
-- strict thread matches above, loose matches on Subject: below --
2017-04-13 13:21 Peter De Schrijver
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