From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755482AbdEDQp1 (ORCPT ); Thu, 4 May 2017 12:45:27 -0400 Received: from mail.skyhub.de ([5.9.137.197]:35404 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753246AbdEDQpV (ORCPT ); Thu, 4 May 2017 12:45:21 -0400 Date: Thu, 4 May 2017 18:45:09 +0200 From: Borislav Petkov To: Radim =?utf-8?B?S3LEjW3DocWZ?= Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Paolo Bonzini , Alexander Graf , "Michael S. Tsirkin" , "Gabriel L. Somlo" Subject: Re: [PATCH 1/4] KVM: svm: prevent MWAIT in guest with erratum 400 Message-ID: <20170504164509.uggp7ff335hnm2zt@pd.tnic> References: <20170503193733.13409-1-rkrcmar@redhat.com> <20170503193733.13409-2-rkrcmar@redhat.com> <20170503201134.fabwojfrqkhime7c@pd.tnic> <20170504140243.GA26642@potion> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20170504140243.GA26642@potion> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 04, 2017 at 04:02:44PM +0200, Radim Krčmář wrote: > X86_BUG_AMD_APIC_C1E doesn't cover C3, which is why I used > X86_BUG_AMD_E400. Practically, the CPUs which even support C3 with E400 are single-core devices and C3 support was removed with revision C3 (yap, the same as the ACPI state) so I think we can safely ignore C3 here. I mean, otherwise, we would be seeing E400 in action as our workaround would not be sufficient. And even then, I don't think we ever go into C3 on those machines as we do HLT which enters C1. > The host uses APIC timer when entering a guest and I assumed that MWAIT > can change C states, but it seems that affected AMD models do not even > support MWAIT hints and the package is in C0 the whole time. Right, we never do MWAIT when idle on AMD but HLT. I notice now that MWAIT text has received recent additions talking about C-state hints but we'd need to evaluate that first and how power consumption behaves and it probably would work the same way as it does on Intel. Thanks. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.