From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752116AbdENGuV (ORCPT ); Sun, 14 May 2017 02:50:21 -0400 Received: from kozue.soulik.info ([108.61.200.231]:47612 "EHLO kozue.soulik.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751124AbdENGuU (ORCPT ); Sun, 14 May 2017 02:50:20 -0400 From: Randy Li To: linux-rockchip@lists.infradead.org Cc: mturquette@baylibre.com, sboyd@codeaurora.org, heiko@sntech.de, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, myy@miouyouyou.fr, Randy Li Subject: [PATCH] clk: rockchip: rk3288: prefer vdpu for vcodec clock source Date: Sun, 14 May 2017 14:50:09 +0800 Message-Id: <20170514065009.3047-1-ayaka@soulik.info> X-Mailer: git-send-email 2.9.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The RK3288 CRU system clock solution would suggest use the vdpu clock source for the VPU(aclk_vpu and hclk_vpu). Reading the registers of VPU(both VEPU and VDPU) would become all high when the vepu is used as the clock source. It may be a bug in the SoC, not sure whether it is fixed at RK3288W. Signed-off-by: Randy Li --- drivers/clk/rockchip/clk-rk3288.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index 68ba7d4..886b249 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -198,7 +198,7 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" }; PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" }; PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" }; -PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vepu", "aclk_vdpu" }; +PNAME(mux_aclk_vcodec_pre_p) = { "aclk_vdpu", "aclk_vepu" }; PNAME(mux_usbphy480m_p) = { "sclk_otgphy1_480m", "sclk_otgphy2_480m", "sclk_otgphy0_480m" }; PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" }; -- 2.9.3