From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932662AbdESV3w (ORCPT ); Fri, 19 May 2017 17:29:52 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39568 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932506AbdESV3o (ORCPT ); Fri, 19 May 2017 17:29:44 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com C3C35C059741 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=jpoimboe@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com C3C35C059741 Date: Fri, 19 May 2017 16:29:13 -0500 From: Josh Poimboeuf To: "H. Peter Anvin" Cc: linux-kernel@vger.kernel.org, Jiri Slaby , Andrew Morton , live-patching@vger.kernel.org, Thomas Gleixner , Ingo Molnar , the arch/x86 maintainers , Andy Lutomirski , Jiri Kosina , Linus Torvalds Subject: Re: [PATCH 7/7] DWARF: add the config option Message-ID: <20170519212913.otir6mlujoxoy3ha@treble> References: <20170505122200.31436-1-jslaby@suse.cz> <20170505122200.31436-7-jslaby@suse.cz> <20170507165524.cdxfuwbd5alr7v6k@treble> <20170519205354.caeyqri2k6gvso3w@treble> <8dbbb971-fc41-fba2-f356-931a7eabe6ef@zytor.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <8dbbb971-fc41-fba2-f356-931a7eabe6ef@zytor.com> User-Agent: Mutt/1.6.0.1 (2016-04-01) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Fri, 19 May 2017 21:29:16 +0000 (UTC) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > How are you handling control flow? Control flow of what? > > Here's the struct in its current state: > > > > #define UNDWARF_REG_UNDEFINED 0 > > #define UNDWARF_REG_CFA 1 > > #define UNDWARF_REG_SP 2 > > #define UNDWARF_REG_FP 3 > > #define UNDWARF_REG_SP_INDIRECT 4 > > #define UNDWARF_REG_FP_INDIRECT 5 > > #define UNDWARF_REG_R10 6 > > #define UNDWARF_REG_DI 7 > > #define UNDWARF_REG_DX 8 > > > > Why only those registers? Also, if you have the option I would really > suggest using the actual x86 register numbers (ax, ex, dx, bx, sp, bp, > si, di, r8-r15 in that order.) Those are the only registers which are ever needed as the base for finding the previous stack frame. 99% of the time it's sp or bp, the other registers are needed for aligned stacks and entry code. Using the actual register numbers isn't an option because I don't need them all and they need to fit in a small number of bits. This construct might be useful for other arches, which is why I called it "FP" instead of "BP". But then I ruined that with the last 3 :-) -- Josh