From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032440AbdEXErp (ORCPT ); Wed, 24 May 2017 00:47:45 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:36125 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S938275AbdEXErd (ORCPT ); Wed, 24 May 2017 00:47:33 -0400 From: Derek Robson To: gilad@benyossef.com, gregkh@linuxfoundation.org Cc: linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, Derek Robson Subject: [PATCH 25/27] Drivers: ccree: cc_regs.h - align block comments Date: Wed, 24 May 2017 16:47:24 +1200 Message-Id: <20170524044724.31024-1-robsonde@gmail.com> X-Mailer: git-send-email 2.12.2 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/cc_regs.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h index 8b89f0603f16..f4b3b5a23ae2 100644 --- a/drivers/staging/ccree/cc_regs.h +++ b/drivers/staging/ccree/cc_regs.h @@ -55,8 +55,9 @@ do { \ BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \ CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE)) -/* yael TBD !!! - * -* all HW includes should start with CC_ and not DX_ !! */ +/* yael TBD !!! + * all HW includes should start with CC_ and not DX_ !! + */ /*! Bit fields set */ @@ -86,10 +87,10 @@ do { \ } while (0) /* Usage example: - u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL)); - CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3); - CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1); - WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow); + * u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL)); + * CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3); + * CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1); + * WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow); */ #endif /*_CC_REGS_H_*/ -- 2.12.2