From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S939796AbdEZEZq (ORCPT ); Fri, 26 May 2017 00:25:46 -0400 Received: from la.guarana.org ([173.254.219.205]:57502 "EHLO la.guarana.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932600AbdEZEZo (ORCPT ); Fri, 26 May 2017 00:25:44 -0400 X-Greylist: delayed 404 seconds by postgrey-1.27 at vger.kernel.org; Fri, 26 May 2017 00:25:44 EDT Date: Fri, 26 May 2017 00:18:53 -0400 From: Kevin Easton To: Andy Lutomirski Cc: Linus Torvalds , "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Message-ID: <20170526041853.GA27213@la.guarana.org> References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 25, 2017 at 05:40:16PM -0700, Andy Lutomirski wrote: > On Thu, May 25, 2017 at 4:24 PM, Linus Torvalds > wrote: > > On Thu, May 25, 2017 at 1:33 PM, Kirill A. Shutemov > > wrote: > >> Here' my first attempt to bring boot-time between 4- and 5-level paging. > >> It looks not too terrible to me. I've expected it to be worse. > > > > If I read this right, you just made it a global on/off thing. > > > > May I suggest possibly a different model entirely? Can you make it a > > per-mm flag instead? > > > > And then we > > > > (a) make all kthreads use the 4-level page tables > > > > (b) which means that all the init code uses the 4-level page tables > > > > (c) which means that all those checks for "start_secondary" etc can > > just go away, because those all run with 4-level page tables. > > > > Or is it just much too expensive to switch between 4-level and 5-level > > paging at run-time? > > > > Even ignoring expensiveness, I'm not convinced it's practical. AFAICT > you can't atomically switch the paging mode and CR3, so either you > need some magic page table with trampoline that works in both modes > (which is presumably doable with some trickery) or you need to flip > paging off. Good luck if an NMI hits in the mean time. There was > code like that once upon a time for EFI mixed mode, but it got deleted > due to triple-faults. According to Intel's documentation you pretty much have to disable paging anyway: "The processor allows software to modify CR4.LA57 only outside of IA-32e mode. In IA-32e mode, an attempt to modify CR4.LA57 using the MOV CR instruction causes a general-protection exception (#GP)." (If it weren't for that, maybe you could point the last entry in the PML4 at the PML4 itself, so it also works as a PML5 for accessing kernel addresses? And of course make sure nothing gets loaded above 0xffffff8000000000). - Kevin