From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751162AbdEaJPu (ORCPT ); Wed, 31 May 2017 05:15:50 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:34303 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751062AbdEaJPp (ORCPT ); Wed, 31 May 2017 05:15:45 -0400 Date: Wed, 31 May 2017 11:15:43 +0200 From: Thomas Petazzoni To: Gregory CLEMENT Cc: Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Andrew Lunn , Jason Cooper , devicetree@vger.kernel.org, Omri Itach , Nadav Haklai , Kostya Porotchkin , Russell King , Rob Herring , Neta Zur Hershkovits , Shadi Ammouri , Marcin Wojtas , linux-arm-kernel@lists.infradead.org, Sebastian Hesselbarth Subject: Re: [PATCH 0/9] Add support for the pin controllers on the Marvell Armada 7K/8K Message-ID: <20170531111543.7c753308@free-electrons.com> In-Reply-To: References: Organization: Free Electrons X-Mailer: Claws Mail 3.13.2 (GTK+ 2.24.30; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, On Fri, 19 May 2017 18:04:42 +0200, Gregory CLEMENT wrote: > Gregory CLEMENT (6): > MAINTAINERS: extend mvebu SoC entry with pinctrl drivers > pinctrl: dt-bindings: add documentation for AP806 pin controllers > pinctrl: dt-bindings: add documentation for CP110 pin controllers > pinctrl: mvebu: remove the offset property for regmap > arm64: marvell: enable the Armada 7K/8K pinctrl driver > arm64: dts: marvell: add pinctrl support for Armada 7K/8K > > Hanna Hawa (2): > pinctrl: mvebu: add driver for Armada AP806 pinctrl > pinctrl: mvebu: add driver for Armada CP110 pinctrl > > Russell King (1): > pinctrl: avoid PLAT_ORION dependency I have tested the combination of your four series (touching clock, pinmux and gpio) on Armada 8K MacchiatoBin, and I was able to validate that the CP110 pinmuxing works as expected. I used MPP37 and MPP38, which I was able to configure as GPIO or I2C0, and validate that they are working as GPIOs and as I2C0. I was however unable to test the AP MPPs due to the lack of access to such pins. Best regards, Thomas -- Thomas Petazzoni, CTO, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com