From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751470AbdEaV7H (ORCPT ); Wed, 31 May 2017 17:59:07 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40289 "EHLO out1-smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751004AbdEaV7F (ORCPT ); Wed, 31 May 2017 17:59:05 -0400 X-ME-Sender: X-Sasl-enc: R19/LZDTHvv8rVuEYFvzb3U0JlhkUW0Ru3ia+a5UKHxg 1496267938 Date: Wed, 31 May 2017 18:58:55 -0300 From: Henrique de Moraes Holschuh To: Peter Zijlstra Cc: tglx@linutronix.de, x86@kernel.org, linux-kernel@vger.kernel.org, kevin.b.stanton@intel.com Subject: Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Message-ID: <20170531215855.GA5382@khazad-dum.debian.net> References: <20170531155201.218077283@infradead.org> <20170531155306.050849877@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170531155306.050849877@infradead.org> X-GPG-Fingerprint1: 4096R/0x0BD9E81139CB4807: C467 A717 507B BAFE D3C1 6092 0BD9 E811 39CB 4807 User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 31 May 2017, Peter Zijlstra wrote: > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014), ... > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), ... > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), > + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), Maybe these revisions need to be decreased by one, so that the SGX behavior of messing with the microcode revision is taken into account? When the processor microcode is auto-updated from the (signed) FIT, and SGX's PRMRR feature is supported, the processor will report its microcode revision as one less. Therefore, a microcode update with revision 0xb2 auto-loaded from FIT would be reported by RDMSR(0x8b) as revision 0xb1. I know about this SGX-related behavior from a coreboot commit from ~two years ago (link below). As far as I can tell, the Intel 64/IA32 SDM is *still* missing any mention about this behavior in vol 3A section 9.11 (where it describes microcode updates). https://review.coreboot.org/cgit/coreboot.git/commit/?id=5042aad4ded1651638ae9b60e34114b65e4f211e -- Henrique Holschuh