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From: Lee Jones <lee.jones@linaro.org>
To: Hans de Goede <hdegoede@redhat.com>
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>,
	Len Brown <lenb@kernel.org>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Mika Westerberg <mika.westerberg@linux.intel.com>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT
Date: Mon, 17 Jul 2017 11:59:19 +0100	[thread overview]
Message-ID: <20170717105919.764zfg3cosoydt6v@dell> (raw)
In-Reply-To: <20170701101346.13578-1-hdegoede@redhat.com>

On Sat, 01 Jul 2017, Hans de Goede wrote:

> Both Bay and Cherry Trail devices may be used together with a Crystal Cove
> PMIC. Each platform has its own variant of the PMIC, which both use the
> same ACPI HID, but they are not 100% compatible.
> 
> Looking at the android x86 kernel sources where most of the Crystal Cove
> code comes from, it talks about "Valley View", "Bay Trail" and / or BYT
> without ever mentioning Cherry Trail, with the exception of the regulator
> driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one
> for Crystal Cove and one for what it calls Crystal Cove Plus. The
> Crystal Cove Plus regulator driver is the only one to mention Cherry
> Trail and that driver uses different register addresses then the
> normal (Bay Trail) Crystal Cove regulator driver, showing that at
> least the regulator register addresses are different.
> 
> The GPIO code should work on both, and the PWM code is known to work on
> both and is necessary for backlight control on some Cherry Trail devices.
> 
> Testing has shown that the ACPI OpRegion code otoh is causing problems
> on Cherry Trail devices, which is not surprising as it deals with the
> regulators and those have different register addresses on CHT.
> 
> Specifically the ACPI OpRegion code causes the external microsd slot on
> a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to
> become unreliable and throw lots of errors.
> 
> This commit replaces the single mfd_cell array currently used for Crystal
> Cove with 2 separate arrays, one for the Bay Trail variant and one for
> the Cherry Trail variant, note that the Cherry Trail version of the array
> only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately
> not included and drivers for the other cells in the Bay Trail cell array
> were never upstreamed.
> 
> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/intel_soc_pmic_core.c |  2 +-
>  drivers/mfd/intel_soc_pmic_core.h |  3 ++-
>  drivers/mfd/intel_soc_pmic_crc.c  | 27 +++++++++++++++++++++++----
>  3 files changed, 26 insertions(+), 6 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

      parent reply	other threads:[~2017-07-17 10:59 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-01 10:13 Hans de Goede
2017-07-01 10:13 ` [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants Hans de Goede
2017-07-02 12:34   ` Andy Shevchenko
2017-07-17 10:59   ` Lee Jones
2017-07-17 13:23     ` Andy Shevchenko
2017-07-18  7:17       ` Lee Jones
2017-07-21 18:41         ` Hans de Goede
2017-07-21 19:23           ` Andy Shevchenko
2017-07-02 12:34 ` [PATCH 1/2] mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT Andy Shevchenko
2017-07-17 10:59 ` Lee Jones [this message]

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