From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751406AbdGRGxf (ORCPT ); Tue, 18 Jul 2017 02:53:35 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:55275 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751026AbdGRGxe (ORCPT ); Tue, 18 Jul 2017 02:53:34 -0400 From: Jisheng Zhang To: , , CC: , , , Jisheng Zhang Subject: [PATCH v2] PCI: dwc: designware: test PCIE_ATU_ENABLE bit to check enabled or not Date: Tue, 18 Jul 2017 14:48:21 +0800 Message-ID: <20170718064821.3668-1-jszhang@marvell.com> X-Mailer: git-send-email 2.13.2 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-07-18_04:,, signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1706020000 definitions=main-1707180113 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ATU CTRL2 register is 32 bit, besides the enable bit, other bits may also be set. To check whether the ATU is enabled or not, we should test the enable bit. Signed-off-by: Jisheng Zhang Acked-by: Joao Pinto --- Since v1: - Add Joao's Ack - Fix typo in commit msg, thank Jingoo drivers/pci/dwc/pcie-designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 0e03af279259..6bf0b409050a 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -177,7 +177,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, */ for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) { val = dw_pcie_readl_dbi(pci, PCIE_ATU_CR2); - if (val == PCIE_ATU_ENABLE) + if (val & PCIE_ATU_ENABLE) return; usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX); -- 2.13.2