From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751800AbdG1Kur (ORCPT ); Fri, 28 Jul 2017 06:50:47 -0400 Received: from mga02.intel.com ([134.134.136.20]:13454 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751681AbdG1Kuq (ORCPT ); Fri, 28 Jul 2017 06:50:46 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,425,1496127600"; d="scan'208";a="292662176" From: Mika Westerberg To: linux-kernel@vger.kernel.org Cc: Lee Jones , Peter Tyser , abdo.roig@gmail.com, Mika Westerberg Subject: [PATCH] mfd: lpc_ich: Do not touch SPI-NOR write protection bit on Haswell/Broadwell Date: Fri, 28 Jul 2017 13:50:42 +0300 Message-Id: <20170728105042.66615-1-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.13.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org At least on Lenovo Thinkpad Yoga, the BIOS seems to monitor the SPI-NOR write protection bit and if it is flipped to read/write it assumes the BIOS configuration was changed on next reboot. It then, for unknown reasons, resets the BIOS settings back to default. We can prevent this by just leaving the write protection bit intact and let the SPI-NOR driver know whether the device is writable or not. In case of this particular Lenovo the SPI-NOR flash will be exposed as read-only. Fixes: ff00d7a32a1b ("mfd: lpc_ich: Add support for SPI serial flash host controller") Link: https://bugzilla.kernel.org/show_bug.cgi?id=195951 Reported-by: Abdó Roig-Marange Signed-off-by: Mika Westerberg --- drivers/mfd/lpc_ich.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 773f1554d2f9..450ae36645aa 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -1119,17 +1119,7 @@ static int lpc_ich_init_spi(struct pci_dev *dev) res->start = spi_base + SPIBASE_LPT; res->end = res->start + SPIBASE_LPT_SZ - 1; - /* - * Try to make the flash chip writeable now by - * setting BCR_WPD. It it fails we tell the driver - * that it can only read the chip. - */ pci_read_config_dword(dev, BCR, &bcr); - if (!(bcr & BCR_WPD)) { - bcr |= BCR_WPD; - pci_write_config_dword(dev, BCR, bcr); - pci_read_config_dword(dev, BCR, &bcr); - } info->writeable = !!(bcr & BCR_WPD); } break; -- 2.13.2