From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752241AbdHOLfO (ORCPT ); Tue, 15 Aug 2017 07:35:14 -0400 Received: from foss.arm.com ([217.140.101.70]:50546 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751148AbdHOLfM (ORCPT ); Tue, 15 Aug 2017 07:35:12 -0400 From: Marc Zyngier To: linux-kernel@vger.kernel.org Cc: Wei Xu , James Hogan , Thomas Gleixner , Jason Cooper , Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Kevin Cernekee , Florian Fainelli , Chris Zankel , Max Filippov , Paul Burton , Matt Redfearn Subject: [PATCH 03/12] irqchip/gic: Report that effective affinity is a single target Date: Tue, 15 Aug 2017 12:34:38 +0100 Message-Id: <20170815113447.14507-4-marc.zyngier@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170815113447.14507-1-marc.zyngier@arm.com> References: <20170815113447.14507-1-marc.zyngier@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The GIC driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-gic.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f1fd5f44d1d4..586929d072ca 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -7,6 +7,7 @@ config ARM_GIC select IRQ_DOMAIN select IRQ_DOMAIN_HIERARCHY select MULTI_IRQ_HANDLER + select GENERIC_IRQ_EFFECTIVE_AFF_MASK config ARM_GIC_PM bool diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 1b1df4f770bd..20dd2ba3d603 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -344,6 +344,8 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, writel_relaxed(val | bit, reg); gic_unlock_irqrestore(flags); + irq_data_update_effective_affinity(d, cpumask_of(cpu)); + return IRQ_SET_MASK_OK_DONE; } #endif @@ -966,6 +968,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, handle_fasteoi_irq, NULL, NULL); irq_set_probe(irq); + irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); } return 0; } -- 2.11.0