From: Alexander Shishkin <alexander.shishkin@linux.intel.com>
To: Greg KH <greg@kroah.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>,
Chunyan Zhang <zhang.chunyan@linaro.org>,
linux-kernel@vger.kernel.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>
Subject: [GIT PULL 08/15] intel_th: msu: Use the real device in case of IOMMU domain allocation
Date: Fri, 25 Aug 2017 19:15:59 +0300 [thread overview]
Message-ID: <20170825161606.2670-9-alexander.shishkin@linux.intel.com> (raw)
In-Reply-To: <20170825161606.2670-1-alexander.shishkin@linux.intel.com>
When allocating DMA buffers for the MSU, use the real device instead
of GTH.
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
---
drivers/hwtracing/intel_th/msu.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/intel_th/msu.c b/drivers/hwtracing/intel_th/msu.c
index dbbe31df74..dfb57eaa9f 100644
--- a/drivers/hwtracing/intel_th/msu.c
+++ b/drivers/hwtracing/intel_th/msu.c
@@ -709,17 +709,17 @@ static int msc_buffer_win_alloc(struct msc *msc, unsigned int nr_blocks)
}
for (i = 0; i < nr_blocks; i++) {
- win->block[i].bdesc = dma_alloc_coherent(msc_dev(msc), size,
- &win->block[i].addr,
- GFP_KERNEL);
+ win->block[i].bdesc =
+ dma_alloc_coherent(msc_dev(msc)->parent->parent, size,
+ &win->block[i].addr, GFP_KERNEL);
+
+ if (!win->block[i].bdesc)
+ goto err_nomem;
#ifdef CONFIG_X86
/* Set the page as uncached */
set_memory_uc((unsigned long)win->block[i].bdesc, 1);
#endif
-
- if (!win->block[i].bdesc)
- goto err_nomem;
}
win->msc = msc;
--
2.14.1
next prev parent reply other threads:[~2017-08-25 16:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-25 16:15 [GIT PULL 00/15] stm class/intel_th: Updates for 4.14 Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 01/15] stm: Potential read overflow in stm_char_policy_set_ioctl() Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 02/15] stm class: Document the stm_ftrace Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 03/15] intel_th: pci: Enable bus mastering Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 04/15] intel_th: Output devices without ports don't need assigning Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 05/15] intel_th: Streamline the subdevice tree accessors Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 06/15] intel_th: Make SOURCE devices children of the root device Alexander Shishkin
2017-08-25 16:15 ` [GIT PULL 07/15] intel_th: Make the switch allocate its subdevices Alexander Shishkin
2017-08-25 16:15 ` Alexander Shishkin [this message]
2017-08-25 16:16 ` [GIT PULL 09/15] intel_th: Enumerate Low Power Path output port type Alexander Shishkin
2017-08-25 16:16 ` [GIT PULL 10/15] intel_th: pti: Support " Alexander Shishkin
2017-08-25 16:16 ` [GIT PULL 11/15] intel_th: pci: Add Cannon Lake PCH-H support Alexander Shishkin
2017-08-25 16:16 ` [GIT PULL 12/15] intel_th: pci: Add Cannon Lake PCH-LP support Alexander Shishkin
2017-08-25 16:16 ` [GIT PULL 13/15] intel_th: pci: Use drvdata for quirks Alexander Shishkin
2017-08-25 16:16 ` [GIT PULL 14/15] intel_th: Add global activate/deactivate callbacks for the glue layers Alexander Shishkin
2017-08-25 16:16 ` [GIT PULL 15/15] intel_th: Perform time resync on capture start Alexander Shishkin
2017-08-28 14:59 ` [GIT PULL 00/15] stm class/intel_th: Updates for 4.14 Greg KH
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