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Peter Anvin" , Ingo Molnar , Peter Zijlstra Subject: [PATCH] kvm/x86: Avoid clearing the C-bit in rsvd_bits() Date: Fri, 25 Aug 2017 15:55:40 -0500 Message-Id: <20170825205540.123531-1-brijesh.singh@amd.com> X-Mailer: git-send-email 2.9.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Originating-IP: [165.204.78.1] X-ClientProxiedBy: MWHPR22CA0072.namprd22.prod.outlook.com (10.171.142.34) To SN1PR12MB0158.namprd12.prod.outlook.com (10.162.3.145) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 597f7e78-2dd8-4f7a-9cbb-08d4ebfbac7d X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(300000503095)(300135400095)(48565401081)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);SRVR:SN1PR12MB0158; X-Microsoft-Exchange-Diagnostics: 1;SN1PR12MB0158;3:sB8dlxs8yx0EawJ2ddRIbTNcibQ3vnHnnO/SeJMdnckFDC3L50yOEih3NLWDZdH6GqY10O0cQageflBnk3tVmSQ/AxZp686DLZfiNEhZZcXwnFaTTFvFYyEBENQKq7aPxszqbcz9hg7eUEjIIBCdvLla4uk+6m8i1P/rRwk/ubrr4NpfQA0vVdRjUjHs3nLQd/eiU5XiOti/PRckrMk+QF9kz8PDHQTiEvptj30Zo5YghRUq3FVhrDCkUrnXr3CM;25:bmXcDI8iIoC4IbB9Q2V25Cif+2zl+gwrkshVWVTyRKDTO1t17cZSJzjD/i44M8gjJfJQi2mcFsOP17wBNST7BWwtiMklkiYREFM07Zu5/bucN0UBnjxcjpBnLe/TGk+H0Mj2a7ZZjXmBFYxgApoBuQqUmmkCXrenGtwwj1b2m2UwQkk31vg3LRx+YwelsTqoi0eQTBNIhRIRR+3fcVN10rtCxh4bOW82o+7Hi8LOkuNfKQ579rsKrNmu/V66neHI2mzRE+4ElSMV2CnsL8gBxgu1wjx1eUNlYOAdjGVDg2X++fkVuQaQe+OD67iGRWIB/9+/F2rgyAwVaxYcKX+WAw==;31:hoGz6trJRfRBh/R7H8p7697iH8VE+5PiuQWDizeSwJNotgr4X3c37yk2Km8ftXDw0QwPjjXv91WP0AIbz4B5YxwvamSU7AscdPbfU+KG0oLMaymu+bnzBZcdnyLXGii1/h/rUyOBWrre5cFlv02FBuEpP7LT70RVJ7TMvSx9c2lCTw7Khb1gxqc7DG4KWqzg6KRuSV/KKKoL946eHmRVgUjTY+FAjA9H97tsNkMY3PI= X-MS-TrafficTypeDiagnostic: SN1PR12MB0158: X-Microsoft-Exchange-Diagnostics: 1;SN1PR12MB0158;20:9jyjmpRjtjMtDSJyae9BrSc4QkHNoYB/igD49JgXps8P4zkHQQwBpMTRX9sysXoxQghaPNqE+PTwftuw4SpUJu4L9jffsmcjHBT9HJ0N06D7VYneClYOdN+5UHbW9mx4mJs9+paqJ9XIj6jir7/kVTGumgbHCTeu2bxaWLYwegep0pf6RllBJqA26bYPV4O2ije82aGwScz6OBQxtySH8TWOLVgkt3rjVEApt0hMUkUFnYJTh7++PpSE/wIt8OfrgEccGQkPp732UPRQsMCeSwzlHwas3KABzP2FXhtg9XkKp8oVwQGWx7xYjSB6t3N+2YW+g5Yr0Fbqt3T4/LmHFAudnso9n3bcHyMkO7bxCMy++akDpZeR5d+uVhMPGDq+y/hIT0SfX31PfEeVi0fxxWkFTCEiXJzXeIVgwr4Bvht/DA5iYFfSTxdJwqDrOcNwSe8vuF7XJEEvIRCJQCOSvdAC7QA1CH+weZKM3orDiHbGZoRiI6nHfSY1L6C2raJk;4:nGmlnPfuedCyjeSUCEdAO1jNeMgHrbPYsLps/3YaPInhn3c5tDdX3wDccNGump+quJtke5Y0MtLuYv7QeJbqHtlewbUZQ3F3E+g7m7aERLvDR2hpqGM+h6VTesVScfuhCFDAbolRXnhD2E8a8xQM/ceiBI1cwXLbaMi9tlYIKerdw87ZyIQKByA+NVy/aKLQKhsFpTzSkfi0lRyb39awpMeYQ4HlmUzozDdtYVU3aR/jjw4AHNJRny2X8xfkB9NX6VTAHvXq1cKHdqrCAcm8+JYRdZlTnT8e12xkeAGAGaI= X-Exchange-Antispam-Report-Test: UriScan:(767451399110); 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Applying a mask based on properties of the host MMU is incorrect. Additionally, the masks computed by __reset_rsvds_bits_mask also apply to guest page tables, where the C bit is reserved since we don't emulate SME. The fix is to clear the C-bit from rsvd_bits_mask array after it has been populated from __reset_rsvds_bits_mask() Acked-by: Paolo Bonzini Cc: Tom Lendacky Cc: Stephen Rothwell Cc: Paolo Bonzini Cc: Radim Krčmář Cc: Thomas Gleixner Cc: H. Peter Anvin Cc: Ingo Molnar Cc: Peter Zijlstra Suggested-by: Paolo Bonzini Fixes: d0ec49d ("kvm/x86/svm: Support Secure Memory Encryption within KVM") Signed-off-by: Brijesh Singh --- arch/x86/kvm/mmu.c | 30 +++++++++++++++++++++++++++--- arch/x86/kvm/mmu.h | 2 +- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c index ccb70b8..04d7508 100644 --- a/arch/x86/kvm/mmu.c +++ b/arch/x86/kvm/mmu.c @@ -4109,16 +4109,28 @@ void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { bool uses_nx = context->nx || context->base_role.smep_andnot_wp; + struct rsvd_bits_validate *shadow_zero_check; + int i; /* * Passing "true" to the last argument is okay; it adds a check * on bit 8 of the SPTEs which KVM doesn't use anyway. */ - __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, + shadow_zero_check = &context->shadow_zero_check; + __reset_rsvds_bits_mask(vcpu, shadow_zero_check, boot_cpu_data.x86_phys_bits, context->shadow_root_level, uses_nx, guest_cpuid_has_gbpages(vcpu), is_pse(vcpu), true); + + if (!shadow_me_mask) + return; + + for (i = context->shadow_root_level; --i >= 0;) { + shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; + } + } EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); @@ -4136,17 +4148,29 @@ static void reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { + struct rsvd_bits_validate *shadow_zero_check; + int i; + + shadow_zero_check = &context->shadow_zero_check; + if (boot_cpu_is_amd()) - __reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check, + __reset_rsvds_bits_mask(vcpu, shadow_zero_check, boot_cpu_data.x86_phys_bits, context->shadow_root_level, false, boot_cpu_has(X86_FEATURE_GBPAGES), true, true); else - __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, + __reset_rsvds_bits_mask_ept(shadow_zero_check, boot_cpu_data.x86_phys_bits, false); + if (!shadow_me_mask) + return; + + for (i = context->shadow_root_level; --i >= 0;) { + shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; + shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; + } } /* diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 3cc7255..d7d248a 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -48,7 +48,7 @@ static inline u64 rsvd_bits(int s, int e) { - return __sme_clr(((1ULL << (e - s + 1)) - 1) << s); + return ((1ULL << (e - s + 1)) - 1) << s; } void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value); -- 2.9.4