From: Peter Zijlstra <peterz@infradead.org>
To: Stafford Horne <shorne@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Openrisc <openrisc@lists.librecores.org>,
Jonas Bonn <jonas@southpole.se>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Subject: Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support
Date: Thu, 31 Aug 2017 09:46:54 +0200 [thread overview]
Message-ID: <20170831074654.aebcc7wvfbv7ebrw@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <1a5c872fdf79d00c84ccd5ba3a5e02d02c1039c6.1504129273.git.shorne@gmail.com>
On Thu, Aug 31, 2017 at 06:58:34AM +0900, Stafford Horne wrote:
> OpenRISC only supports hardware instructions that perform 4 byte atomic
> operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte
> implementations are needed. To do this we leverage the 4 byte atomic
> operations and shift/mask the 1 and 2 byte areas as needed.
>
> This heavily borrows ideas and routines from sh and mips, which do
> something similar.
Is there value in lifting them into something common?
next prev parent reply other threads:[~2017-08-31 7:47 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
2017-08-30 21:58 ` [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-09-01 8:02 ` [OpenRISC] " Geert Uytterhoeven
2017-09-01 8:03 ` Geert Uytterhoeven
2017-09-01 8:26 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
2017-09-01 8:06 ` [OpenRISC] " Geert Uytterhoeven
2017-09-01 8:28 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-08-31 7:46 ` Peter Zijlstra [this message]
2017-08-31 9:01 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
2017-08-31 9:28 ` Marc Zyngier
2017-09-01 1:24 ` Stafford Horne
2017-09-01 17:25 ` Marc Zyngier
2017-09-03 22:12 ` Stafford Horne
2017-09-04 7:35 ` Marc Zyngier
2017-08-31 10:59 ` Mark Rutland
2017-09-01 13:59 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 06/13] openrisc: initial SMP support Stafford Horne
2017-08-30 22:02 ` [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-08-30 22:02 ` [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-08-30 22:02 ` [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-08-30 22:03 ` [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-08-31 10:41 ` Mark Rutland
2017-08-31 13:05 ` Stafford Horne
2017-09-11 22:37 ` Pavel Machek
2017-09-11 22:55 ` Stafford Horne
2017-09-12 7:47 ` Pavel Machek
2017-09-12 22:15 ` Stafford Horne
2017-08-30 22:03 ` [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-08-30 22:03 ` [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-08-30 22:03 ` [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne
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