From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751937AbdHaNzg (ORCPT ); Thu, 31 Aug 2017 09:55:36 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:33298 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751742AbdHaNwi (ORCPT ); Thu, 31 Aug 2017 09:52:38 -0400 X-Google-Smtp-Source: ADKCNb76d+7IVl1D40QkWhJn8MjuTUljZH5cwvDC8Pmmzl0nQrxSk+EAYSujSBxDf4UoJ11N/6T/yg== From: Jerome Brunet To: Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/9] ARM64: dts: meson-gxl: libretech-cc: enable high speed modes Date: Thu, 31 Aug 2017 15:52:23 +0200 Message-Id: <20170831135226.19784-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170831135226.19784-1-jbrunet@baylibre.com> References: <20170831135226.19784-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable sdcard UHS modes up to SDR50. Unfortunately, it seems the PCB of the libretech-cc cannot handle SDR104 at 200Mhz reliably. Also enable eMMC DDR52 mode. Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 7d252168c2fa..64c54c92e214 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -205,6 +205,9 @@ bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; max-frequency = <100000000>; disable-wp; @@ -224,6 +227,7 @@ bus-width = <8>; cap-mmc-highspeed; + mmc-ddr-3_3v; max-frequency = <50000000>; non-removable; disable-wp; -- 2.9.5