From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752071AbdIAL73 (ORCPT ); Fri, 1 Sep 2017 07:59:29 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:35248 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751715AbdIAL6S (ORCPT ); Fri, 1 Sep 2017 07:58:18 -0400 X-Google-Smtp-Source: ADKCNb4C9W07TLTBu9xUQ+H2cDcjG28YzqBeNEZz/lTOuM1qYWDuG20B9ryMwsZPIH0VZgOc7xoRoQ== From: Corentin Labbe To: andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v2 4/5] net: mdio-mux-mmioreg: Can handle 8/16/32 bits registers Date: Fri, 1 Sep 2017 13:56:03 +0200 Message-Id: <20170901115604.27513-5-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170901115604.27513-1-clabbe.montjoie@gmail.com> References: <20170901115604.27513-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fix an old information that mdio-mux-mmioreg can only handle 8bit registers. This is not true anymore. Signed-off-by: Corentin Labbe Reviewed-by: Andrew Lunn --- drivers/net/phy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 5afe6fdcc968..a9d16a3af514 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -85,7 +85,7 @@ config MDIO_BUS_MUX_MMIOREG parent bus. Child bus selection is under the control of one of the FPGA's registers. - Currently, only 8-bit registers are supported. + Currently, only 8/16/32 bits registers are supported. config MDIO_CAVIUM tristate -- 2.13.5