From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Chen-Yu Tsai <wens@csie.org>,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH 0/2] clk: sunxi-ng: Add several flags to H3 CCU
Date: Wed, 13 Sep 2017 20:42:41 +0200 [thread overview]
Message-ID: <20170913184241.b3dypwygczkfxrvx@flea.lan> (raw)
In-Reply-To: <20170910124006.60250-1-icenowy@aosc.io>
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On Sun, Sep 10, 2017 at 08:40:04PM +0800, Icenowy Zheng wrote:
> The H3 CCU is the earliest driver that uses sunxi-ng clk framework, and
> some problems show when doing further development.
>
> This patchset fixes some issues by add several clock flags.
>
> The first patch solves the problem that setting some PLL before ungating
> them will trigger timeout for waiting for lock by adds CLK_SET_RATE_UNGATE
> flag.
>
> The second patch solves the problem that H3 GPU clock is not really tweaked
> by add CLK_SET_RATE_PARENT flag to it.
Queued both for 4.15, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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prev parent reply other threads:[~2017-09-13 18:42 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-10 12:40 Icenowy Zheng
2017-09-10 12:40 ` [PATCH 1/2] clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs Icenowy Zheng
2017-09-10 12:40 ` [PATCH 2/2] clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock Icenowy Zheng
2017-09-13 18:42 ` Maxime Ripard [this message]
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