From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751803AbdIUSNU (ORCPT ); Thu, 21 Sep 2017 14:13:20 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:58508 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751636AbdIUSNS (ORCPT ); Thu, 21 Sep 2017 14:13:18 -0400 From: "Guilherme G. Piccoli" To: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, corbet@lwn.net, "Guilherme G. Piccoli" Subject: [PATCH] Documentation: rewrite confusing statement about memory barriers Date: Thu, 21 Sep 2017 15:13:10 -0300 X-Mailer: git-send-email 2.14.1 X-TM-AS-GCONF: 00 x-cbid: 17092118-0024-0000-0000-000002D5F185 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00007774; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000231; SDB=6.00920339; UDB=6.00462450; IPR=6.00700561; BA=6.00005601; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00017238; XFM=3.00000015; UTC=2017-09-21 18:13:15 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17092118-0025-0000-0000-0000457FC300 Message-Id: <20170921181310.7272-1-gpiccoli@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-09-21_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000 definitions=main-1709210246 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In this specific portion of the write memory barriers description, the documentation mentions sequential order of stores, which is confusing since sequential ordering is not guaranteed. This patch tries to improve the doc in order to avoid any mis-understanding. Signed-off-by: Guilherme G. Piccoli --- Documentation/memory-barriers.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index b759a60624fd..a4bbbd1b63a0 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -383,8 +383,8 @@ Memory barriers come in four basic varieties: to have any effect on loads. A CPU can be viewed as committing a sequence of store operations to the - memory system as time progresses. All stores before a write barrier will - occur in the sequence _before_ all the stores after the write barrier. + memory system as time progresses. All stores _before_ a write barrier + will occur _before_ all the stores after the write barrier. [!] Note that write barriers should normally be paired with read or data dependency barriers; see the "SMP barrier pairing" subsection. -- 2.14.1