From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751906AbdI1ISb (ORCPT ); Thu, 28 Sep 2017 04:18:31 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:45818 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751129AbdI1IS3 (ORCPT ); Thu, 28 Sep 2017 04:18:29 -0400 X-Google-Smtp-Source: AOwi7QAh8ly20pUXo1GAyAOSC0xpIbGPfoyfaaJy2Y9PeFnHtCjzJpKiV3Xczr6DNbZd4sFIjbylsg== Date: Thu, 28 Sep 2017 10:18:25 +0200 From: Ingo Molnar To: "Kirill A. Shutemov" Cc: Ingo Molnar , Linus Torvalds , x86@kernel.org, Thomas Gleixner , "H. Peter Anvin" , Andrew Morton , Andy Lutomirski , Cyrill Gorcunov , Borislav Petkov , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCHv7 06/19] x86/boot/compressed/64: Detect and handle 5-level paging at boot-time Message-ID: <20170928081825.mq3gccldrgbvjlnc@gmail.com> References: <20170918105553.27914-1-kirill.shutemov@linux.intel.com> <20170918105553.27914-7-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170918105553.27914-7-kirill.shutemov@linux.intel.com> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Kirill A. Shutemov wrote: > This patch prepare decompression code to boot-time switching between 4- > and 5-level paging. > > Signed-off-by: Kirill A. Shutemov > --- > arch/x86/boot/compressed/head_64.S | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S > index b4a5d284391c..09c85e8558eb 100644 > --- a/arch/x86/boot/compressed/head_64.S > +++ b/arch/x86/boot/compressed/head_64.S > @@ -288,6 +288,28 @@ ENTRY(startup_64) > leaq boot_stack_end(%rbx), %rsp > > #ifdef CONFIG_X86_5LEVEL > + /* Preserve rbx across cpuid */ > + movq %rbx, %r8 > + > + /* Check if leaf 7 is supported */ > + xorl %eax, %eax > + cpuid > + cmpl $7, %eax > + jb lvl5 > + > + /* > + * Check if la57 is supported. > + * The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16] > + */ > + movl $7, %eax > + xorl %ecx, %ecx > + cpuid > + andl $(1 << 16), %ecx > + jz lvl5 > + > + /* Restore rbx */ In (new) x86 asm code we refer to registers in capital letters. Also, CPUID should be capitalized consistently as well. Also, LA57 should be capitalized as well. > + movq %r8, %rbx > + > /* Check if 5-level paging has already enabled */ > movq %cr4, %rax BTW., please also fix the typo in this comment while at it. Thanks, Ingo