From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753116AbdI1O2O (ORCPT ); Thu, 28 Sep 2017 10:28:14 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:33678 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752017AbdI1O2M (ORCPT ); Thu, 28 Sep 2017 10:28:12 -0400 X-Google-Smtp-Source: AOwi7QB4Oitw28M0DXhnrOkfqw1KAdS9GhJDbi+ODO8XD30ZHhukHfrqlg7osd9bmPA2H90ywW58NA== Date: Thu, 28 Sep 2017 17:28:09 +0300 From: "Kirill A. Shutemov" To: Ingo Molnar Cc: "Kirill A. Shutemov" , Ingo Molnar , Linus Torvalds , x86@kernel.org, Thomas Gleixner , "H. Peter Anvin" , Andrew Morton , Andy Lutomirski , Cyrill Gorcunov , Borislav Petkov , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCHv7 12/19] x86/mm: Adjust virtual address space layout in early boot. Message-ID: <20170928142809.3ste5znjtjmucwig@node.shutemov.name> References: <20170918105553.27914-1-kirill.shutemov@linux.intel.com> <20170918105553.27914-13-kirill.shutemov@linux.intel.com> <20170928083155.7qahecaeifz5em5f@gmail.com> <20170928132608.priml7nc7dmo5r6d@node.shutemov.name> <20170928133838.oa72tybvmyy3sfgw@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20170928133838.oa72tybvmyy3sfgw@gmail.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 28, 2017 at 03:38:38PM +0200, Ingo Molnar wrote: > > * Kirill A. Shutemov wrote: > > > On Thu, Sep 28, 2017 at 10:31:55AM +0200, Ingo Molnar wrote: > > > > > > * Kirill A. Shutemov wrote: > > > > > > > We need to adjust virtual address space to support switching between > > > > paging modes. > > > > > > > > The adjustment happens in __startup_64(). > > > > > > > +#ifdef CONFIG_X86_5LEVEL > > > > + if (__read_cr4() & X86_CR4_LA57) { > > > > + pgtable_l5_enabled = 1; > > > > + pgdir_shift = 48; > > > > + ptrs_per_p4d = 512; > > > > + } > > > > +#endif > > > > > > So CR4 really sucks as a parameter passing interface - was it us who enabled LA57 > > > in the early boot code, right? Couldn't we add a flag which gets set there, or > > > something? > > > > It's not necessary that we enabled LA57. At least I tried to write code > > that doesn't assume this. We enable it if bootloader haven't done this > > already for us. > > > > What is so awful about using CR4 as passing interface? It's one-time > > check, so performance shouldn't be an issue. > > As a starter, this code is in generic x86 code [choose_random_location()], is this > CR4 bit known to AMD as well and is it guaranteed to be sane across all x86 CPUs? > I don't think so. It's architectural thing, so it's consistent across all x86 implementations. > CR4 is a poor interface to pass CPU features through. Generaly we try to enumerate > CPU features via CPUID, and/or enable synthetic CPU features in certain cases, and > work from there. Okay, has_cpuflag(X86_FEATURE_LA57) seems would do. -- Kirill A. Shutemov