From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752123AbdJDNEF (ORCPT ); Wed, 4 Oct 2017 09:04:05 -0400 Received: from mail.kernel.org ([198.145.29.99]:48772 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751910AbdJDNEE (ORCPT ); Wed, 4 Oct 2017 09:04:04 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 54A6121883 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=goodmis.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=rostedt@goodmis.org Date: Wed, 4 Oct 2017 09:04:01 -0400 From: Steven Rostedt To: Peter Zijlstra Cc: pmladek@suse.com, sergey.senozhatsky@gmail.com, linux-kernel@vger.kernel.org, mingo@kernel.org, tglx@linutronix.de, "Paul E. McKenney" Subject: Re: [PATCH 3/3] early_printk: Add simple serialization to early_vprintk() Message-ID: <20171004090401.3a5123a6@gandalf.local.home> In-Reply-To: <20171004090830.p5kwzu6ex2wimh4v@hirez.programming.kicks-ass.net> References: <20170928121823.430053219@infradead.org> <20170928122513.431444176@infradead.org> <20171003182422.025d0a67@gandalf.local.home> <20171004090830.p5kwzu6ex2wimh4v@hirez.programming.kicks-ass.net> X-Mailer: Claws Mail 3.14.0 (GTK+ 2.24.31; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 4 Oct 2017 11:08:30 +0200 Peter Zijlstra wrote: > On Tue, Oct 03, 2017 at 06:24:22PM -0400, Steven Rostedt wrote: > > On Thu, 28 Sep 2017 14:18:26 +0200 > > Peter Zijlstra wrote: > > > static int early_vprintk(const char *fmt, va_list args) > > > { > > > + int n, cpu, old; > > > char buf[512]; > > > + > > > + cpu = get_cpu(); > > > + /* > > > + * Test-and-Set inter-cpu spinlock with recursion. > > > + */ > > > + for (;;) { > > > + /* > > > + * c-cas to avoid the exclusive bouncing on spin. > > > + * Depends on the memory barrier implied by cmpxchg > > > + * for ACQUIRE semantics. > > > + */ > > > + old = READ_ONCE(early_printk_cpu); > > > + if (old == -1) { > > > > If old != -1 and old != cpu, is it possible that the CPU could have > > fetched an old value, and never try to fetch it again? > > What? If old != -1 and old != cpu, we'll hit the cpu_relax() and do the > READ_ONCE() again. The READ_ONCE() guarantees we'll do the load again, > as does the barrier() implied by cpu_relax(). I'm more worried about other architectures that don't have as strong of a cache coherency. [ Added Paul as he knows a lot about odd architectures ] Is there any architecture that we support that can have the following: CPU0 CPU1 ---- ---- early_printk_cpu = 1 for (;;) old = READ_ONCE(early_printk_cpu); [ old = 1 ] early_printk_cpu = -1 [...] cpu_relax(); old = READ_ONCE(early_printk_cpu); [ but the CPU uses the cache and not the memory? ] old = 1; -- Steve > > > The cmpxchg memory barrier only happens when old == -1. > > Yeah, so? > > > > + old = cmpxchg(&early_printk_cpu, -1, cpu); > > > + if (old == -1) > > > + break; > > > + } > > > + /* > > > + * Allow recursion for interrupts and the like. > > > + */ > > > + if (old == cpu) > > > + break; > > > + > > > + cpu_relax(); > > > + } > > > > > > n = vscnprintf(buf, sizeof(buf), fmt, args); > > > early_console->write(early_console, buf, n); > > > > > > + /* > > > + * Unlock -- in case @old == @cpu, this is a no-op. > > > + */ > > > + smp_store_release(&early_printk_cpu, old); > > > + put_cpu(); > > > + > > > return n; > > > }