[PATCH 0/5] x86/platform/UV: Update TSC support

[<mike.travis@hpe.com>]

The UV BIOS goes to considerable effort to get the TSC synchronization
accurate across the entire system.  Included in that are multiple chassis
that can have 32+ sockets.  The architecture does support an external
high resolution clock to aid in maintaining this synchronization.

The resulting TSC accuracy set by the UV system BIOS is much better
than the generic kernel TSC ADJUST functions.  This is important for
applications that read the TSC values directly for accessing data bases.

*   Patch 1 disables an assumption made by the kernel tsc sync functions
    that Socket 0 in the system should all have a TSC ADJUST value of
    zero.  This is not correct when the chassis are reset asynchronously
    to each other so which TSC's should be zero is not predictable.

*   Patch 2 prevents the kernel from attempting to fix the TSC if the
    system BIOS has determined that the TSC is not stable.  This prevents
    a slew of useless warning messages.

*   Patch 3 eliminates another avalanche of warning messages from older
    BIOS that did not have the TSC ADJUST MSR (ex. >3000 msgs in a 32
    socket Skylake system).  It now notes this with a single warning
    message and then moves on with fixing them.

*   Patch 4 puts in a facility to disable ART if the art to tsc conversion
    factor is not constant for all sockets.

*   Patch 5 puts a new check in the UV system init to check this new BIOS
    flag that displays the result of the TSC synchronization phase.  Three
    possible states are available, "sync is valid", "sync is unstable", or
    TSC sync state is unavailable in this BIOS.  In the later case, the
    UV kernel init reverts to prior assumptions about TSC sync state.

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