From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751917AbdJEWOJ (ORCPT ); Thu, 5 Oct 2017 18:14:09 -0400 Received: from mail-oi0-f66.google.com ([209.85.218.66]:47599 "EHLO mail-oi0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751369AbdJEWOH (ORCPT ); Thu, 5 Oct 2017 18:14:07 -0400 X-Google-Smtp-Source: AOwi7QA7fJCBW0i8XewpLaurHncU5j1kgwnon2yd0O0v/Sz5cAdmUN1fmjSTsgi0ul1HkixwIMVrqA== Date: Thu, 5 Oct 2017 17:14:05 -0500 From: Rob Herring To: Manu Gautam Cc: Kishon Vijay Abraham I , Felipe Balbi , linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, Mark Rutland , Stephen Boyd , Vivek Gautam , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Subject: Re: [PATCH v2 12/17] dt-bindings: phy-qcom-qmp: Update bindings for QMP V3 USB PHY Message-ID: <20171005221405.pnxoskfxtfvygrgm@rob-hp-laptop> References: <1506502753-27408-1-git-send-email-mgautam@codeaurora.org> <1506502753-27408-13-git-send-email-mgautam@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1506502753-27408-13-git-send-email-mgautam@codeaurora.org> User-Agent: NeoMutt/20170113 (1.7.2) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 27, 2017 at 02:29:08PM +0530, Manu Gautam wrote: > Update compatible string and clock names for QMP version V3 > USB PHY. > > Signed-off-by: Manu Gautam > --- > Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > index b6a9f2b..dcf1b8f 100644 > --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt > @@ -8,7 +8,8 @@ Required properties: > - compatible: compatible list, contains: > "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 > "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, > - "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996. > + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, > + "qcom,qmp-v3-usb3-phy" for USB3 QMP V3 phy. This is fine, but you will still need an SoC specific compatible in addition to this. Acked-by: Rob Herring Rob