From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753787AbdJGWsC (ORCPT ); Sat, 7 Oct 2017 18:48:02 -0400 Received: from fldsmtpe03.verizon.com ([140.108.26.142]:3598 "EHLO fldsmtpe03.verizon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753511AbdJGWiV (ORCPT ); Sat, 7 Oct 2017 18:38:21 -0400 From: "Levin, Alexander (Sasha Levin)" Cc: Ding Tianhong , Mark Rutland , Daniel Lezcano , "Levin, Alexander (Sasha Levin)" X-Host: mariner.tdc.vzwcorp.com To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH review for 4.9 22/50] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Thread-Topic: [PATCH review for 4.9 22/50] clocksource/drivers/arm_arch_timer: Add dt binding for hisilicon-161010101 erratum Thread-Index: AQHTP7zEUehRdGYDtU+qNiyFI1uQRA== Date: Sat, 7 Oct 2017 22:36:51 +0000 Message-ID: <20171007223636.24797-22-alexander.levin@verizon.com> References: <20171007223636.24797-1-alexander.levin@verizon.com> In-Reply-To: <20171007223636.24797-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] Content-Type: text/plain; charset="iso-8859-1" MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by nfs id v97Mm86v029780 From: Ding Tianhong [ Upstream commit 729e55225b1f6225ee7a2a358d5141a3264627c4 ] This erratum describes a bug in logic outside the core, so MIDR can't be used to identify its presence, and reading an SoC-specific revision register from common arch timer code would be awkward. So, describe it in the device tree. Signed-off-by: Ding Tianhong Acked-by: Rob Herring Signed-off-by: Mark Rutland Signed-off-by: Daniel Lezcano Signed-off-by: Sasha Levin --- Documentation/devicetree/bindings/arm/arch_timer.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt index ad440a2b8051..e926aea1147d 100644 --- a/Documentation/devicetree/bindings/arm/arch_timer.txt +++ b/Documentation/devicetree/bindings/arm/arch_timer.txt @@ -31,6 +31,12 @@ to deliver its interrupts via SPIs. This also affects writes to the tval register, due to the implicit counter read. +- hisilicon,erratum-161010101 : A boolean property. Indicates the + presence of Hisilicon erratum 161010101, which says that reading the + counters is unreliable in some cases, and reads may return a value 32 + beyond the correct value. This also affects writes to the tval + registers, due to the implicit counter read. + ** Optional properties: - arm,cpu-registers-not-fw-configured : Firmware does not initialize -- 2.11.0