From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753330AbdJLKfu (ORCPT ); Thu, 12 Oct 2017 06:35:50 -0400 Received: from mail-dm3nam03on0040.outbound.protection.outlook.com ([104.47.41.40]:52704 "EHLO NAM03-DM3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752620AbdJLKfg (ORCPT ); Thu, 12 Oct 2017 06:35:36 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Ganapatrao.Kulkarni@cavium.com; From: Ganapatrao Kulkarni To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Will.Deacon@arm.com, catalin.marinas@arm.com, mark.rutland@arm.com, acme@kernel.org, alexander.shishkin@linux.intel.com, peterz@infradead.org, mingo@redhat.com, jnair@caviumnetworks.com, zhangshaokun@hisilicon.com, Jonathan.Cameron@huawei.com, Robert.Richter@cavium.com, gklkml16@gmail.com Subject: [PATCH v7 4/4] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events Date: Thu, 12 Oct 2017 16:04:19 +0530 Message-Id: <20171012103419.29824-5-ganapatrao.kulkarni@cavium.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20171012103419.29824-1-ganapatrao.kulkarni@cavium.com> References: <20171012103419.29824-1-ganapatrao.kulkarni@cavium.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [111.93.218.67] X-ClientProxiedBy: MA1PR0101CA0024.INDPRD01.PROD.OUTLOOK.COM (52.134.136.162) To BN3PR07MB2562.namprd07.prod.outlook.com (10.167.4.151) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 68620c80-d9c1-4fdb-2867-08d5115cf7ff X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254152)(2017052603199)(201703131423075)(201703031133081)(201702281549075);SRVR:BN3PR07MB2562; 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Signed-off-by: Ganapatrao Kulkarni --- tools/perf/pmu-events/arch/arm64/mapfile.csv | 15 ++++++ .../arch/arm64/thunderx2/thunderx2-imp-def.json | 62 ++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/thunderx2-imp-def.json diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv new file mode 100644 index 0000000..7167086 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -0,0 +1,15 @@ +# Format: +# MIDR,Version,JSON/file/pathname,Type +# +# where +# MIDR Processor version +# Variant[23:20] and Revision [3:0] should be zero. +# Version could be used to track version of of JSON file +# but currently unused. +# JSON/file/pathname is the path to JSON file, relative +# to tools/perf/pmu-events/arch/arm64/. +# Type is core, uncore etc +# +# +#Family-model,Version,Filename,EventType +0x00000000420f5160,v1,thunderx2,core diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/thunderx2/thunderx2-imp-def.json new file mode 100644 index 0000000..2db45c4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/thunderx2/thunderx2-imp-def.json @@ -0,0 +1,62 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "l1d_cache_rd", + "BriefDescription": "L1D cache read", + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write ", + "EventCode": "0x41", + "EventName": "l1d_cache_wr", + "BriefDescription": "L1D cache write", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "l1d_cache_refill_rd", + "BriefDescription": "L1D cache refill read", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "l1d_cache_refill_wr", + "BriefDescription": "L1D refill write", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "l1d_tlb_refill_rd", + "BriefDescription": "L1D tlb refill read", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "l1d_tlb_refill_wr", + "BriefDescription": "L1D tlb refill write", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "l1d_tlb_rd", + "BriefDescription": "L1D tlb read", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "l1d_tlb_wr", + "BriefDescription": "L1D tlb write", + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "bus_access_rd", + "BriefDescription": "Bus access read", + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "bus_access_wr", + "BriefDescription": "Bus access write", + } +] -- 2.9.4