From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756195AbdJPTTZ (ORCPT ); Mon, 16 Oct 2017 15:19:25 -0400 Received: from mga14.intel.com ([192.55.52.115]:25851 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756151AbdJPTTX (ORCPT ); Mon, 16 Oct 2017 15:19:23 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,387,1503385200"; d="scan'208";a="1231444235" From: Jarkko Sakkinen To: intel-sgx-kernel-dev@lists.01.org Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Haim Cohen , Jarkko Sakkinen Subject: [PATCH v4 05/12] x86: add SGX MSRs to msr-index.h Date: Mon, 16 Oct 2017 22:18:48 +0300 Message-Id: <20171016191855.16964-6-jarkko.sakkinen@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171016191855.16964-1-jarkko.sakkinen@linux.intel.com> References: <20171016191855.16964-1-jarkko.sakkinen@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Haim Cohen These MSRs hold the SHA256 checksum of the currently configured launch enclave public key. Signed-off-by: Haim Cohen Signed-off-by: Jarkko Sakkinen --- arch/x86/include/asm/msr-index.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index b35cb98b5d60..22e27d46d046 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -436,6 +436,7 @@ #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) #define FEATURE_CONTROL_SGX_ENABLE (1<<18) +#define FEATURE_CONTROL_SGX_LAUNCH_CONTROL_ENABLE (1<<17) #define FEATURE_CONTROL_LMCE (1<<20) #define MSR_IA32_APICBASE 0x0000001b @@ -502,6 +503,12 @@ #define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) #define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) +/* Intel SGX MSRs */ +#define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C +#define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D +#define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E +#define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F + /* Thermal Thresholds Support */ #define THERM_INT_THRESHOLD0_ENABLE (1 << 15) #define THERM_SHIFT_THRESHOLD0 8 -- 2.14.1