From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754145AbdJQMZL convert rfc822-to-8bit (ORCPT ); Tue, 17 Oct 2017 08:25:11 -0400 Received: from smtprelay06.ispgateway.de ([80.67.31.103]:57228 "EHLO smtprelay06.ispgateway.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751609AbdJQMZJ (ORCPT ); Tue, 17 Oct 2017 08:25:09 -0400 Date: Tue, 17 Oct 2017 14:25:07 +0200 From: Lothar =?UTF-8?B?V2HDn21hbm4=?= To: Thierry Reding Cc: David Airlie , Mark Rutland , Rob Herring , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 4/9] drm/panel: simple: add support for overriding the pixel clock polarity Message-ID: <20171017142507.127f1711@karo-electronics.de> In-Reply-To: <20171017121422.GE684@ulmo> References: <1507721021-28174-1-git-send-email-LW@KARO-electronics.de> <1507721021-28174-5-git-send-email-LW@KARO-electronics.de> <20171017121422.GE684@ulmo> Organization: Ka-Ro electronics GmbH MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT X-Df-Sender: bHdAa2Fyby1lbGVjdHJvbmljcy5kZQ== Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tue, 17 Oct 2017 14:14:22 +0200 Thierry Reding wrote: > On Wed, Oct 11, 2017 at 01:23:36PM +0200, Lothar Waßmann wrote: > > The Ka-Ro electronics MB7 baseboard has an on-board LCD->LVDS > > converter that requires a fixed pixelclk polarity, no matter what the > > panel's display_mode specifies. Add an option to override the pixelclk > > polarity defined in the panel's display_mode via DTB. > > I'd argue that the LCD->LVDS converter should be modelled specifically > in DT to handle this case. It could be a implemented as a DRM bridge > driver, for example. > IMO that's just overkill for a simple chip that is in no way configurable nor detectable by software. Lothar Waßmann