From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753552AbdJSRQZ (ORCPT ); Thu, 19 Oct 2017 13:16:25 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:58008 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752690AbdJSRQU (ORCPT ); Thu, 19 Oct 2017 13:16:20 -0400 From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, rob.walker@arm.com, mike.leach@linaro.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, Suzuki K Poulose Subject: [PATCH 01/17] coresight etr: Disallow perf mode temporarily Date: Thu, 19 Oct 2017 18:15:37 +0100 Message-Id: <20171019171553.24056-2-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171019171553.24056-1-suzuki.poulose@arm.com> References: <20171019171553.24056-1-suzuki.poulose@arm.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We don't support ETR in perf mode yet. Temporarily fail the operation until we add proper support. Cc: Mathieu Poirier Signed-off-by: Suzuki K Poulose --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 28 ++----------------------- 1 file changed, 2 insertions(+), 26 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 68fbc8f7450e..d0208f01afd9 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -192,32 +192,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) static int tmc_enable_etr_sink_perf(struct coresight_device *csdev) { - int ret = 0; - unsigned long flags; - struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - - spin_lock_irqsave(&drvdata->spinlock, flags); - if (drvdata->reading) { - ret = -EINVAL; - goto out; - } - - /* - * In Perf mode there can be only one writer per sink. There - * is also no need to continue if the ETR is already operated - * from sysFS. - */ - if (drvdata->mode != CS_MODE_DISABLED) { - ret = -EINVAL; - goto out; - } - - drvdata->mode = CS_MODE_PERF; - tmc_etr_enable_hw(drvdata); -out: - spin_unlock_irqrestore(&drvdata->spinlock, flags); - - return ret; + /* We don't support perf mode yet ! */ + return -EINVAL; } static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode) -- 2.13.6