From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752046AbdJ0DXQ (ORCPT ); Thu, 26 Oct 2017 23:23:16 -0400 Received: from mail-oi0-f43.google.com ([209.85.218.43]:54744 "EHLO mail-oi0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751483AbdJ0DXN (ORCPT ); Thu, 26 Oct 2017 23:23:13 -0400 X-Google-Smtp-Source: ABhQp+Spwj7yO7N+mssSviS8sg9EnkqbHyXIHHK6c8YjyElDWRy2Ivg8jadVB3z59wQMaQTVIwJWbg== Date: Thu, 26 Oct 2017 22:23:11 -0500 From: Rob Herring To: Weiyi Lu Cc: Matthias Brugger , Stephen Boyd , Mike Turquette , James Liao , Fan Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com Subject: Re: [PATCH v6 2/9] clk: mediatek: Add dt-bindings for MT2712 clocks Message-ID: <20171027032311.2am3x3fbrdxwr5oj@rob-hp-laptop> References: <1508731840-4231-1-git-send-email-weiyi.lu@mediatek.com> <1508731840-4231-3-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1508731840-4231-3-git-send-email-weiyi.lu@mediatek.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 23, 2017 at 12:10:33PM +0800, Weiyi Lu wrote: > Add MT2712 clock dt-bindings, include topckgen, apmixedsys, > infracfg, pericfg, mcucfg and subsystem clocks. > > Signed-off-by: Weiyi Lu > --- > include/dt-bindings/clock/mt2712-clk.h | 427 +++++++++++++++++++++++++++++++++ > 1 file changed, 427 insertions(+) > create mode 100644 include/dt-bindings/clock/mt2712-clk.h Acked-by: Rob Herring