From: Mikko Perttunen <mperttunen@nvidia.com>
To: thierry.reding@gmail.com, jonathanh@nvidia.com
Cc: digetx@gmail.com, dri-devel@lists.freedesktop.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
Mikko Perttunen <mperttunen@nvidia.com>
Subject: [PATCH 01/10] gpu: host1x: Parameterize channel aperture size
Date: Sun, 5 Nov 2017 13:01:09 +0200 [thread overview]
Message-ID: <20171105110118.15142-2-mperttunen@nvidia.com> (raw)
In-Reply-To: <20171105110118.15142-1-mperttunen@nvidia.com>
The size of a single channel's aperture is different on Tegra186 vs.
previous chips. Parameterize the value using a new define in the
register definition headers.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
drivers/gpu/host1x/hw/channel_hw.c | 3 +--
drivers/gpu/host1x/hw/hw_host1x01_channel.h | 2 ++
drivers/gpu/host1x/hw/hw_host1x02_channel.h | 2 ++
drivers/gpu/host1x/hw/hw_host1x04_channel.h | 2 ++
drivers/gpu/host1x/hw/hw_host1x05_channel.h | 2 ++
drivers/gpu/host1x/hw/hw_host1x06_vm.h | 2 ++
6 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 5c0dc6bb51d1..246b78c41281 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -26,7 +26,6 @@
#include "../intr.h"
#include "../job.h"
-#define HOST1X_CHANNEL_SIZE 16384
#define TRACE_MAX_LENGTH 128U
static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo,
@@ -205,7 +204,7 @@ static void enable_gather_filter(struct host1x *host,
static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev,
unsigned int index)
{
- ch->regs = dev->regs + index * HOST1X_CHANNEL_SIZE;
+ ch->regs = dev->regs + HOST1X_CHANNEL_BASE(index);
enable_gather_filter(dev, ch);
return 0;
}
diff --git a/drivers/gpu/host1x/hw/hw_host1x01_channel.h b/drivers/gpu/host1x/hw/hw_host1x01_channel.h
index b4bc7ca4e051..be56a3a506de 100644
--- a/drivers/gpu/host1x/hw/hw_host1x01_channel.h
+++ b/drivers/gpu/host1x/hw/hw_host1x01_channel.h
@@ -51,6 +51,8 @@
#ifndef __hw_host1x_channel_host1x_h__
#define __hw_host1x_channel_host1x_h__
+#define HOST1X_CHANNEL_BASE(x) ((x) * 0x4000)
+
static inline u32 host1x_channel_fifostat_r(void)
{
return 0x0;
diff --git a/drivers/gpu/host1x/hw/hw_host1x02_channel.h b/drivers/gpu/host1x/hw/hw_host1x02_channel.h
index e490bcde33fe..a142576a2c6e 100644
--- a/drivers/gpu/host1x/hw/hw_host1x02_channel.h
+++ b/drivers/gpu/host1x/hw/hw_host1x02_channel.h
@@ -51,6 +51,8 @@
#ifndef HOST1X_HW_HOST1X02_CHANNEL_H
#define HOST1X_HW_HOST1X02_CHANNEL_H
+#define HOST1X_CHANNEL_BASE(x) ((x) * 0x4000)
+
static inline u32 host1x_channel_fifostat_r(void)
{
return 0x0;
diff --git a/drivers/gpu/host1x/hw/hw_host1x04_channel.h b/drivers/gpu/host1x/hw/hw_host1x04_channel.h
index 2e8b635aa660..645483c07fc2 100644
--- a/drivers/gpu/host1x/hw/hw_host1x04_channel.h
+++ b/drivers/gpu/host1x/hw/hw_host1x04_channel.h
@@ -51,6 +51,8 @@
#ifndef HOST1X_HW_HOST1X04_CHANNEL_H
#define HOST1X_HW_HOST1X04_CHANNEL_H
+#define HOST1X_CHANNEL_BASE(x) ((x) * 0x4000)
+
static inline u32 host1x_channel_fifostat_r(void)
{
return 0x0;
diff --git a/drivers/gpu/host1x/hw/hw_host1x05_channel.h b/drivers/gpu/host1x/hw/hw_host1x05_channel.h
index abbbc2641ce6..6aef6bc1c96d 100644
--- a/drivers/gpu/host1x/hw/hw_host1x05_channel.h
+++ b/drivers/gpu/host1x/hw/hw_host1x05_channel.h
@@ -51,6 +51,8 @@
#ifndef HOST1X_HW_HOST1X05_CHANNEL_H
#define HOST1X_HW_HOST1X05_CHANNEL_H
+#define HOST1X_CHANNEL_BASE(x) ((x) * 0x4000)
+
static inline u32 host1x_channel_fifostat_r(void)
{
return 0x0;
diff --git a/drivers/gpu/host1x/hw/hw_host1x06_vm.h b/drivers/gpu/host1x/hw/hw_host1x06_vm.h
index e54b33902332..0750aea78a30 100644
--- a/drivers/gpu/host1x/hw/hw_host1x06_vm.h
+++ b/drivers/gpu/host1x/hw/hw_host1x06_vm.h
@@ -15,6 +15,8 @@
*
*/
+#define HOST1X_CHANNEL_BASE(x) ((x) * 0x100)
+
#define HOST1X_CHANNEL_DMASTART 0x0000
#define HOST1X_CHANNEL_DMASTART_HI 0x0004
#define HOST1X_CHANNEL_DMAPUT 0x0008
--
2.14.2
next prev parent reply other threads:[~2017-11-05 11:04 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-05 11:01 [PATCH 00/10] Dynamic Host1x channel allocation Mikko Perttunen
2017-11-05 11:01 ` Mikko Perttunen [this message]
2017-11-05 11:01 ` [PATCH 02/10] gpu: host1x: Print MLOCK state in debug dumps on T186 Mikko Perttunen
2017-11-05 11:01 ` [PATCH 03/10] gpu: host1x: Add lock around channel allocation Mikko Perttunen
2017-11-05 11:01 ` [PATCH 04/10] gpu: host1x: Lock classes during job submission Mikko Perttunen
2017-11-05 16:46 ` Dmitry Osipenko
2017-11-07 12:28 ` Mikko Perttunen
2017-11-07 21:23 ` Dmitry Osipenko
2017-12-05 13:21 ` Mikko Perttunen
2017-12-05 13:43 ` Dmitry Osipenko
2017-11-05 11:01 ` [PATCH 05/10] gpu: host1x: Add job done callback Mikko Perttunen
2017-11-05 11:01 ` [PATCH 06/10] drm/tegra: Deliver job completion callback to client Mikko Perttunen
2017-11-16 16:33 ` Dmitry Osipenko
2017-11-16 16:40 ` Dmitry Osipenko
2017-11-29 9:09 ` Mikko Perttunen
2017-11-05 11:01 ` [PATCH 07/10] drm/tegra: Make syncpoints be per-context Mikko Perttunen
2017-11-05 11:01 ` [PATCH 08/10] drm/tegra: Implement dynamic channel allocation model Mikko Perttunen
2017-11-05 17:43 ` Dmitry Osipenko
2017-11-07 12:29 ` Mikko Perttunen
2017-11-13 11:49 ` Dmitry Osipenko
2017-11-05 11:01 ` [PATCH 09/10] drm/tegra: Boot VIC in runtime resume Mikko Perttunen
2017-11-05 11:01 ` [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel Mikko Perttunen
2017-11-05 17:14 ` Dmitry Osipenko
2017-11-07 13:11 ` Mikko Perttunen
2017-11-07 15:29 ` Dmitry Osipenko
2017-11-10 21:15 ` Dmitry Osipenko
2017-11-12 11:23 ` Dmitry Osipenko
2017-11-29 9:10 ` Mikko Perttunen
2017-11-29 12:18 ` Dmitry Osipenko
2017-11-29 12:25 ` Mikko Perttunen
2017-11-29 12:37 ` Dmitry Osipenko
2017-11-07 15:34 ` [PATCH 00/10] Dynamic Host1x channel allocation Dmitry Osipenko
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