From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753321AbdKGFhp (ORCPT ); Tue, 7 Nov 2017 00:37:45 -0500 Received: from mail-sh2.amlogic.com ([58.32.228.45]:12247 "EHLO mail-sh2.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753226AbdKGFhi (ORCPT ); Tue, 7 Nov 2017 00:37:38 -0500 From: Yixun Lan To: Neil Armstrong , Jerome Brunet , Martin Blumenstingl CC: Carlo Caione , Kevin Hilman , Yixun Lan , Xingyu Chen , , , Subject: [PATCH v3 3/4] dt-bindings: iio: adc: update the doc for SAR ADC Date: Tue, 7 Nov 2017 13:37:17 +0800 Message-ID: <20171107053717.31948-2-yixun.lan@amlogic.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171107053717.31948-1-yixun.lan@amlogic.com> References: <20171107053717.31948-1-yixun.lan@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.18.20.76] Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xingyu Chen Update the doc as the SAR ADC modules doesn't require "sana" clock. Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt index f413e82c8b83..1e6ee3deb4fa 100644 --- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt +++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt @@ -15,7 +15,6 @@ Required properties: - "clkin" for the reference clock (typically XTAL) - "core" for the SAR ADC core clock optional clocks: - - "sana" for the analog clock - "adc_clk" for the ADC (sampling) clock - "adc_sel" for the ADC (sampling) clock mux - vref-supply: the regulator supply for the ADC reference voltage -- 2.14.1