From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752319AbdKJJRK (ORCPT ); Fri, 10 Nov 2017 04:17:10 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:37650 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751130AbdKJJRH (ORCPT ); Fri, 10 Nov 2017 04:17:07 -0500 X-Google-Smtp-Source: AGs4zMb2mXpJW1E7xXxsGU//Qk3beIy1SvthCC9bKEzMv+2RPAZJ3HH5LyPaM5k3MLGbaNEfs586Ag== Date: Fri, 10 Nov 2017 10:17:03 +0100 From: Ingo Molnar To: "Kirill A. Shutemov" Cc: Ingo Molnar , Linus Torvalds , x86@kernel.org, Thomas Gleixner , "H. Peter Anvin" , Andy Lutomirski , Cyrill Gorcunov , Borislav Petkov , Andi Kleen , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 3/4] x86/boot/compressed/64: Introduce place_trampoline() Message-ID: <20171110091703.7izzr7p3jkyxh7vd@gmail.com> References: <20171101115503.18358-1-kirill.shutemov@linux.intel.com> <20171101115503.18358-4-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171101115503.18358-4-kirill.shutemov@linux.intel.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Kirill A. Shutemov wrote: > If bootloader enables 64-bit mode with 4-level paging, we need to > switch over to 5-level paging. The switching requires disabling paging. > It works fine if kernel itself is loaded below 4G. > > If bootloader put the kernel above 4G (not sure if anybody does this), > we would loose control as soon as paging is disabled as code becomes > unreachable. > > To handle the situation, we need a trampoline in lower memory that would > take care about switching on 5-level paging. > > Apart from trampoline itself we also need place to store top level page > table in lower memory as we don't have a way to load 64-bit value into > CR3 from 32-bit mode. We only really need 8-bytes there as we only use > the very first entry of the page table. But we allocate whole page > anyway. We cannot have the code in the same because, there's hazard that > a CPU would read page table speculatively and get confused seeing > garbage. > > This patch introduces place_trampoline() that finds right spot in lower > memory for trampoline, copies trampoline code there and setups new top > level page table for 5-level paging. > > At this point we do all the preparation, but not yet use trampoline. > It will be done in following patch. > > Signed-off-by: Kirill A. Shutemov > --- > arch/x86/boot/compressed/head_64.S | 13 +++++++++++ > arch/x86/boot/compressed/pagetable.c | 42 ++++++++++++++++++++++++++++++++++++ > arch/x86/boot/compressed/pagetable.h | 18 ++++++++++++++++ > 3 files changed, 73 insertions(+) > create mode 100644 arch/x86/boot/compressed/pagetable.h > > diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S > index 6ac8239af2b6..4d1555b39de0 100644 > --- a/arch/x86/boot/compressed/head_64.S > +++ b/arch/x86/boot/compressed/head_64.S > @@ -315,6 +315,18 @@ ENTRY(startup_64) > * The first step is go into compatibility mode. > */ > > + /* > + * Find suitable place for trampoline and populate it. > + * The address will be stored in RCX. > + * > + * RSI holds real mode data and need to be preserved across > + * a function call. > + */ > + pushq %rsi > + call place_trampoline > + popq %rsi > + movq %rax, %rcx > + > /* Clear additional page table */ > leaq lvl5_pgtable(%rbx), %rdi > xorq %rax, %rax One request: it's always going to be fragile if the _only_ thing that uses the trampoline is the 5-level paging code. Could we use the trampoline in the 4-level paging case too? It's not required, but would test much of the trampoline allocation and copying machinery - and the performance cost is negligible. Thanks, Ingo