From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755321AbdKNNFU (ORCPT ); Tue, 14 Nov 2017 08:05:20 -0500 Received: from shards.monkeyblade.net ([184.105.139.130]:40602 "EHLO shards.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755139AbdKNNFN (ORCPT ); Tue, 14 Nov 2017 08:05:13 -0500 Date: Tue, 14 Nov 2017 22:05:09 +0900 (KST) Message-Id: <20171114.220509.510877965546682781.davem@davemloft.net> To: niklas.cassel@axis.com Cc: peppe.cavallaro@st.com, alexandre.torgue@st.com, niklass@axis.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next v2] net: stmmac: fix LPI transitioning for dwmac4 From: David Miller In-Reply-To: <20171114101555.18902-1-niklas.cassel@axis.com> References: <20171114101555.18902-1-niklas.cassel@axis.com> X-Mailer: Mew version 6.7 on Emacs 25.3 / Mule 6.0 (HANACHIRUSATO) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.5.12 (shards.monkeyblade.net [149.20.54.216]); Tue, 14 Nov 2017 05:05:13 -0800 (PST) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Niklas Cassel Date: Tue, 14 Nov 2017 11:15:54 +0100 > The LPI transitioning logic in stmmac_main uses > priv->tx_path_in_lpi_mode to enter/exit LPI. > > However, priv->tx_path_in_lpi_mode is assigned > using the return value from host_irq_status(). > > So for dwmac4, priv->tx_path_in_lpi_mode was always false, > so stmmac_tx_clean() would always try to put us in eee mode, > and stmmac_xmit() would never take us out of eee mode. > > To fix this, make host_irq_status() read and return the LPI > irq status also for dwmac4. > > This also increments the existing LPI counters, so that > ethtool --statistics shows LPI transitions also for dwmac4. > > For dwmac1000, irqs are enabled/disabled using the register > named "Interrupt Mask Register", and thus setting a bit disables > that specific irq. > > For dwmac4 the matching register is named "MAC_Interrupt_Enable", > and thus setting a bit enables that specific irq. > > Looking at dwmac1000_core.c, the irqs that are always enabled are: > LPI and PMT. > > Looking at dwmac4_core.c, the irqs that are always enabled are: > PMT. > > To be able to read the LPI irq status, we need to enable the LPI > irq also for dwmac4. > > Signed-off-by: Niklas Cassel Applied.