From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752756AbdKTTuw (ORCPT ); Mon, 20 Nov 2017 14:50:52 -0500 Received: from mail-pg0-f68.google.com ([74.125.83.68]:33410 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752705AbdKTTui (ORCPT ); Mon, 20 Nov 2017 14:50:38 -0500 X-Google-Smtp-Source: AGs4zMbBqZx/wFmwi4L0/2M2+dKxlQlZkM/BusQP5tYHFKcHOA61vdgZgLoFrgWfLFhUXCOjgtVmaQ== Subject: [PATCH] dt-bindings: Add an enable method to RISC-V Date: Mon, 20 Nov 2017 11:50:22 -0800 Message-Id: <20171120195022.2307-1-palmer@sifive.com> X-Mailer: git-send-email 2.13.6 Cc: patches@groups.riscv.org, linux-kernel@vger.kernel.org, Palmer Dabbelt From: Palmer Dabbelt To: mark.rutland@arm.com, robh+dt@kernel.org, devicetree@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RISC-V doesn't currently specify a mechanism for enabling or disabling CPUs. Instead, we assume that all CPUs are enabled on boot, and if someone wants to save power we instead put a CPU to sleep via a WFI loop. This patch adds "enable-method" to the RISC-V CPU binding, which currently only has the value "none". This allows us to change the enable method in the future. CC: Mark Rutland Signed-off-by: Palmer Dabbelt --- Documentation/devicetree/bindings/riscv/cpus.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt index adf7b7af5dc3..dd9e1ae197e2 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.txt +++ b/Documentation/devicetree/bindings/riscv/cpus.txt @@ -82,6 +82,11 @@ described below. Value type: Definition: Contains the RISC-V ISA string of this hart. These ISA strings are defined by the RISC-V ISA manual. + - cpu-enable-method: + Usage: required + Value type: + Definition: Must be one of + "none": This CPU's state cannot be changed. Example: SiFive Freedom U540G Development Kit --------------------------------------------- @@ -105,6 +110,7 @@ Linux is allowed to run on. reg = <0>; riscv,isa = "rv64imac"; status = "disabled"; + enable-method = "none"; L10: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -130,6 +136,7 @@ Linux is allowed to run on. reg = <1>; riscv,isa = "rv64imafdc"; status = "okay"; + enable-method = "none"; tlb-split; L13: interrupt-controller { #interrupt-cells = <1>; -- 2.13.6