From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752268AbdKZP6m (ORCPT ); Sun, 26 Nov 2017 10:58:42 -0500 Received: from mail-wr0-f173.google.com ([209.85.128.173]:40265 "EHLO mail-wr0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751181AbdKZP6l (ORCPT ); Sun, 26 Nov 2017 10:58:41 -0500 X-Google-Smtp-Source: AGs4zMbM6SX4KwId8fET7bJ7xK8VE4AK1GMPBTWPS/jEElOL4NEUQe7W4imspWzPmcQHWx8qhl+DxQ== Date: Sun, 26 Nov 2017 16:58:37 +0100 From: Ingo Molnar To: Andy Lutomirski Cc: Dave Hansen , X86 ML , Borislav Petkov , "linux-kernel@vger.kernel.org" , Brian Gerst , Linus Torvalds Subject: Re: [PATCH v2] x86/entry: Fix assumptions that the HW TSS is at the beginning of cpu_tss Message-ID: <20171126155837.ludnd6va4rqy5d37@gmail.com> References: <03fb20a8639aeecfeda3ba18a520ce646267eb9a.1510371795.git.luto@kernel.org> <2fdf9cf9-ec48-e63f-2ec8-44160c206c9a@intel.com> <20171126134844.o4nz6kuuzsflxrw6@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org * Andy Lutomirski wrote: > On Sun, Nov 26, 2017 at 5:48 AM, Ingo Molnar wrote: > > > > * Dave Hansen wrote: > > > >> On 11/10/2017 08:05 PM, Andy Lutomirski wrote: > >> > -struct tss_struct doublefault_tss __cacheline_aligned = { > >> > - .x86_tss = { > >> > - .sp0 = STACK_START, > >> > - .ss0 = __KERNEL_DS, > >> > - .ldt = 0, > >> ... > >> > +struct x86_hw_tss doublefault_tss __cacheline_aligned = { > >> > + .sp0 = STACK_START, > >> > + .ss0 = __KERNEL_DS, > >> > + .ldt = 0, > >> > + .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, > >> > >> FWIW, I really like the trend of renaming the hardware structures in > >> such a way that it's clear that they *are* hardware structures. > >> > >> It might also be nice to reference the relevant SDM sections on the > >> topic, or even to include a comment along the lines of how it get used. > >> This chunk from the SDM is particularly relevant: > >> > >> "The TSS holds information important to 64-bit mode and that is not > >> directly related to the task-switch mechanism." > > > > That makes sense - I've updated this patch with the following description added to > > struct x86_hw_tss: > > I've folded this in along with all the reviews so far, and a few misc > fixes from Boris' review. I was planning to resend the whole series > today after I track down the kbuild error. Does that sound good? Could you please do a delta to the very latest WIP.x86/mm instead? In the latest I have included the review tags already, and all the easy-to-do review feedback as well, so the delta should be rasonably small. These entry bits are destined for x86/urgent real soon, so Thomas and me are trying to pin the tree down and do delta changes only. If it's a simple full interdiff between your latest and WIP.x86/mm that's fine as well, can backmerge everything accordingly. Thanks, Ingo