From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751790AbdK0Kg3 (ORCPT ); Mon, 27 Nov 2017 05:36:29 -0500 Received: from mail.skyhub.de ([5.9.137.197]:53126 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751277AbdK0Kg2 (ORCPT ); Mon, 27 Nov 2017 05:36:28 -0500 Date: Mon, 27 Nov 2017 11:36:19 +0100 From: Borislav Petkov To: Yazen Ghannam Cc: linux-edac@vger.kernel.org, Borislav Petkov , Tony Luck , x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems Message-ID: <20171127103619.h5dddkdbps4aysat@pd.tnic> References: <20171120162646.5210-1-Yazen.Ghannam@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20171120162646.5210-1-Yazen.Ghannam@amd.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 20, 2017 at 10:26:46AM -0600, Yazen Ghannam wrote: > From: Yazen Ghannam > > The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR, > is used on SMCA systems to set the LVT offset for the Threshold and > Deferred error interrupts. > > This register was used on non-SMCA systems to also set the Deferred > interrupt type in bits 2:1. However, these bits are reserved on SMCA > systems. > > Only set MSRC000_0410[2:1] on non-SMCA systems. > > Signed-off-by: Yazen Ghannam > --- > arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c > index e4e27adedc81..32008a8d293f 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c > +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c > @@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c) > (deferred_error_int_vector != amd_deferred_error_interrupt)) > deferred_error_int_vector = amd_deferred_error_interrupt; > > - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; > + if (!mce_flags.smca) > + low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC; > + > wrmsr(MSR_CU_DEF_ERR, low, high); > } > > -- Applied, thanks. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.