From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932319AbdK0S7A (ORCPT ); Mon, 27 Nov 2017 13:59:00 -0500 Received: from smtprelay4.synopsys.com ([198.182.47.9]:34740 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932176AbdK0S4X (ORCPT ); Mon, 27 Nov 2017 13:56:23 -0500 From: Eugeniy Paltsev To: linux-snps-arc@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Vineet Gupta , Alexey Brodkin , Eugeniy Paltsev Subject: [PATCH 1/4] ARC: [plat-hsdk]: Set initial core pll output frequency Date: Mon, 27 Nov 2017 21:56:08 +0300 Message-Id: <20171127185611.12379-2-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com> References: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set initial core pll output frequency specified in device tree to 1GHz. It will be applied at the core pll driver probing. Signed-off-by: Eugeniy Paltsev --- arch/arc/boot/dts/hsdk.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts index 8f627c2..006aa3d 100644 --- a/arch/arc/boot/dts/hsdk.dts +++ b/arch/arc/boot/dts/hsdk.dts @@ -114,6 +114,14 @@ reg = <0x00 0x10>, <0x14B8 0x4>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 1GHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <1000000000>; }; serial: serial@5000 { -- 2.9.3