From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754704AbdK2Mck (ORCPT ); Wed, 29 Nov 2017 07:32:40 -0500 Received: from bombadil.infradead.org ([65.50.211.133]:34968 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753747AbdK2Mci (ORCPT ); Wed, 29 Nov 2017 07:32:38 -0500 Date: Wed, 29 Nov 2017 13:31:58 +0100 From: Peter Zijlstra To: linux-kernel@vger.kernel.org, Thomas Gleixner Cc: Dave Hansen , Andy Lutomirski , Ingo Molnar , Borislav Petkov , Brian Gerst , Denys Vlasenko , "H. Peter Anvin" , Josh Poimboeuf , Linus Torvalds , Rik van Riel , daniel.gruss@iaik.tugraz.at, hughd@google.com, keescook@google.com, linux-mm@kvack.org, michael.schwarz@iaik.tugraz.at, moritz.lipp@iaik.tugraz.at, richard.fellner@student.tugraz.at, Andy Lutomirski Subject: Re: [PATCH 4/6] x86/mm/kaiser: Support PCID without INVPCID Message-ID: <20171129123158.xqgiusjamnt2udag@hirez.programming.kicks-ass.net> References: <20171129103301.131535445@infradead.org> <20171129103512.819130098@infradead.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171129103512.819130098@infradead.org> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 29, 2017 at 11:33:05AM +0100, Peter Zijlstra wrote: > @@ -220,7 +215,27 @@ For 32-bit we have the following convent > .macro SWITCH_TO_USER_CR3 scratch_reg:req > STATIC_JUMP_IF_FALSE .Lend_\@, kaiser_enabled_key, def=1 > mov %cr3, \scratch_reg > - ADJUST_USER_CR3 \scratch_reg > + > + /* > + * Test if the ASID needs a flush. > + */ > + push \scratch_reg /* preserve CR3 */ So I was just staring at disasm of a few functions and I noticed this one reads like push, while others read like pushq. So does the stupid assembler thing really do a 32bit push if you provide it with a 64bit register? > + andq $(0x7FF), \scratch_reg /* mask ASID */ > + bt \scratch_reg, PER_CPU_VAR(user_asid_flush_mask) > + jnc .Lnoflush_\@ > + > + /* Flush needed, clear the bit */ > + btr \scratch_reg, PER_CPU_VAR(user_asid_flush_mask) > + pop \scratch_reg /* original CR3 */ > + jmp .Ldo_\@ > + > +.Lnoflush_\@: > + pop \scratch_reg /* original CR3 */ > + ALTERNATIVE "", "bts $63, \scratch_reg", X86_FEATURE_PCID > + > +.Ldo_\@: > + /* Flip the PGD and ASID to the user version */ > + orq $(KAISER_SWITCH_MASK), \scratch_reg > mov \scratch_reg, %cr3 > .Lend_\@: > .endm