From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753013AbdK2U42 (ORCPT ); Wed, 29 Nov 2017 15:56:28 -0500 Received: from mga03.intel.com ([134.134.136.65]:47282 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751783AbdK2U40 (ORCPT ); Wed, 29 Nov 2017 15:56:26 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,339,1508828400"; d="scan'208";a="181713520" Date: Wed, 29 Nov 2017 12:56:24 -0800 From: Andi Kleen To: Jim Mattson Cc: Wanpeng Li , LKML , kvm list , Paolo Bonzini , Radim =?utf-8?B?S3LEjW3DocWZ?= , Wanpeng Li Subject: Re: [PATCH] KVM: VMX: Cache IA32_DEBUGCTL in memory Message-ID: <20171129205624.GD3070@tassilo.jf.intel.com> References: <1511935673-7371-1-git-send-email-wanpeng.li@hotmail.com> <87fu8xj69o.fsf@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.1 (2017-09-22) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Nov 29, 2017 at 11:05:46AM -0800, Jim Mattson wrote: > An alternative is to give the L1 guest read permission for this MSR in > the MSR permission bitmaps. It's still going to be ~80 cycles, but > that's better than the cost of a VM-exit/VM-entry round-trip. It's a useful optimization, 80 cycles is 80 cycles. The cache invalidation could likely be really simple, like: have a global counter always check the counter before and after and don't use the cache if they don't match. change KDB etc. to increase the counter. -Andi