From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756345AbdLGPwa (ORCPT ); Thu, 7 Dec 2017 10:52:30 -0500 Received: from fldsmtpe03.verizon.com ([140.108.26.142]:44488 "EHLO fldsmtpe03.verizon.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756293AbdLGPwY (ORCPT ); Thu, 7 Dec 2017 10:52:24 -0500 From: alexander.levin@verizon.com Cc: =?utf-8?B?TWljaGHFgiBNaXJvc8WCYXc=?= , "Thierry Reding" , alexander.levin@verizon.com X-Host: mariner.tdc.vzwcorp.com To: "linux-kernel@vger.kernel.org" , "stable@vger.kernel.org" Subject: [PATCH AUTOSEL for 4.9 116/156] clk: tegra: Fix cclk_lp divisor register Thread-Topic: [PATCH AUTOSEL for 4.9 116/156] clk: tegra: Fix cclk_lp divisor register Thread-Index: AQHTb3L0LThZujnhTkmxSBNa6o21/A== Date: Thu, 7 Dec 2017 15:49:24 +0000 Message-ID: <20171207154845.4814-116-alexander.levin@verizon.com> References: <20171207154845.4814-1-alexander.levin@verizon.com> In-Reply-To: <20171207154845.4814-1-alexander.levin@verizon.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.144.60.250] Content-Type: text/plain; charset="utf-8" Content-ID: <97F25834BB410F4F930DAE92EFD3974F@vzwcorp.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id vB7H3OB0021699 From: Michał Mirosław [ Upstream commit 54eff2264d3e9fd7e3987de1d7eba1d3581c631e ] According to comments in code and common sense, cclk_lp uses its own divisor, not cclk_g's. Fixes: b08e8c0ecc42 ("clk: tegra: add clock support for Tegra30") Signed-off-by: Michał Mirosław Acked-By: Peter De Schrijver Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 8e2db5ead8da..af520d81525f 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -963,7 +963,7 @@ static void __init tegra30_super_clk_init(void) * U71 divider of cclk_lp. */ clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", - clk_base + SUPER_CCLKG_DIVIDER, 0, + clk_base + SUPER_CCLKLP_DIVIDER, 0, TEGRA_DIVIDER_INT, 16, 8, 1, NULL); clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); -- 2.11.0