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From: "Kirill A. Shutemov" <kirill@shutemov.name>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
	x86@kernel.org, Linus Torvalds <torvalds@linux-foundation.org>,
	Andy Lutomirsky <luto@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Dave Hansen <dave.hansen@intel.com>,
	Borislav Petkov <bpetkov@suse.de>,
	Greg KH <gregkh@linuxfoundation.org>,
	keescook@google.com, hughd@google.com,
	Brian Gerst <brgerst@gmail.com>,
	Josh Poimboeuf <jpoimboe@redhat.com>,
	Denys Vlasenko <dvlasenk@redhat.com>,
	Rik van Riel <riel@redhat.com>,
	Boris Ostrovsky <boris.ostrovsky@oracle.com>,
	Juergen Gross <jgross@suse.com>,
	David Laight <David.Laight@aculab.com>,
	Eduardo Valentin <eduval@amazon.com>,
	aliguori@amazon.com, Will Deacon <will.deacon@arm.com>,
	daniel.gruss@iaik.tugraz.at, Kees Cook <keescook@chromium.org>,
	Borislav Petkov <bp@alien8.de>
Subject: Re: [patch V149 38/50] x86/pti: Put the LDT in its own PGD if PTI is on
Date: Sun, 17 Dec 2017 14:09:34 +0300	[thread overview]
Message-ID: <20171217110934.f34h6i6yht5vpe4f@node.shutemov.name> (raw)
In-Reply-To: <20171216213139.549001406@linutronix.de>

On Sat, Dec 16, 2017 at 10:24:32PM +0100, Thomas Gleixner wrote:
> From: Andy Lutomirski <luto@kernel.org>
> 
> With PTI enabled, the LDT must be mapped in the usermode tables somewhere.
> The LDT is per process, i.e. per mm.
> 
> An earlier approach mapped the LDT on context switch into a fixmap area,
> but that's a big overhead and exhausted the fixmap space when NR_CPUS got
> big.
> 
> Take advantage of the fact that there is an address space hole which
> provides a completely unused pgd. Use this pgd to manage per-mm LDT
> mappings.
> 
> This has a down side: the LDT isn't (currently) randomized, and an attack
> that can write the LDT is instant root due to call gates (thanks, AMD, for
> leaving call gates in AMD64 but designing them wrong so they're only useful
> for exploits).  This can be mitigated by making the LDT read-only or
> randomizing the mapping, either of which is strightforward on top of this
> patch.
> 
> This will significantly slow down LDT users, but that shouldn't matter for
> important workloads -- the LDT is only used by DOSEMU(2), Wine, and very
> old libc implementations.
> 
> [ tglx: Decrapified it ]
> 
> Signed-off-by: Andy Lutomirski <luto@kernel.org>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Cc: Kees Cook <keescook@chromium.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Brian Gerst <brgerst@gmail.com>
> Cc: Dave Hansen <dave.hansen@intel.com>
> Cc: David Laight <David.Laight@aculab.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: "Kirill A. Shutemov" <kirill@shutemov.name>
> 
> ---
>  Documentation/x86/x86_64/mm.txt         |    3 
>  arch/x86/include/asm/mmu_context.h      |   55 +++++++++++-
>  arch/x86/include/asm/pgtable_64_types.h |    4 
>  arch/x86/include/asm/processor.h        |   23 +++--
>  arch/x86/kernel/ldt.c                   |  139 +++++++++++++++++++++++++++++++-
>  arch/x86/mm/dump_pagetables.c           |   12 ++
>  6 files changed, 219 insertions(+), 17 deletions(-)
> 
> --- a/Documentation/x86/x86_64/mm.txt
> +++ b/Documentation/x86/x86_64/mm.txt
> @@ -12,6 +12,7 @@ ffffea0000000000 - ffffeaffffffffff (=40
>  ... unused hole ...
>  ffffec0000000000 - fffffbffffffffff (=44 bits) kasan shadow memory (16TB)
>  ... unused hole ...
> +fffffe8000000000 - fffffeffffffffff (=39 bits) LDT remap for PTI
>  ffffff0000000000 - ffffff7fffffffff (=39 bits) %esp fixup stacks
>  ... unused hole ...
>  ffffffef00000000 - fffffffeffffffff (=64 GB) EFI region mapping space
> @@ -28,7 +29,7 @@ ffffffffffe00000 - ffffffffffffffff (=2
>  hole caused by [56:63] sign extension
>  ff00000000000000 - ff0fffffffffffff (=52 bits) guard hole, reserved for hypervisor
>  ff10000000000000 - ff8fffffffffffff (=55 bits) direct mapping of all phys. memory
> -ff90000000000000 - ff9fffffffffffff (=52 bits) hole
> +ff90000000000000 - ff9fffffffffffff (=49 bits) LDT remap for PTI

  +ff90000000000000 - ff9fffffffffffff (=52 bits) LDT remap for PTI

-- 
 Kirill A. Shutemov

  reply	other threads:[~2017-12-17 11:09 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-16 21:23 [patch V149 00/50] x86/pti: Updated and reshuffled patch queue Thomas Gleixner
2017-12-16 21:23 ` [patch V149 01/50] x86/mm/dump_pagetables: Check PAGE_PRESENT for real Thomas Gleixner
2017-12-16 21:23 ` [patch V149 02/50] x86/vsyscall/64: Explicitly set _PAGE_USER in the pagetable hierarchy Thomas Gleixner
2017-12-16 21:23 ` [patch V149 03/50] x86/vsyscall/64: Warn and fail vsyscall emulation in NATIVE mode Thomas Gleixner
2017-12-16 21:23 ` [patch V149 04/50] arch: Allow arch_dup_mmap() to fail Thomas Gleixner
2017-12-16 21:23 ` [patch V149 05/50] x86/ldt: Rework locking Thomas Gleixner
2017-12-16 21:24 ` [patch V149 06/50] x86/ldt: Prevent ldt inheritance on exec Thomas Gleixner
2017-12-16 21:24 ` [patch V149 07/50] x86/mm/64: Improve the memory map documentation Thomas Gleixner
2017-12-16 21:24 ` [patch V149 08/50] x86/doc: Remove obvious weirdness Thomas Gleixner
2017-12-16 21:24 ` [patch V149 09/50] x86/entry: Remove SYSENTER_stack naming Thomas Gleixner
2017-12-16 21:24 ` [patch V149 10/50] x86/uv: Use the right tlbflush API Thomas Gleixner
2017-12-16 21:24 ` [patch V149 11/50] x86/microcode: Dont abuse the tlbflush interface Thomas Gleixner
2017-12-16 21:24 ` [patch V149 12/50] x86/mm: Use __flush_tlb_one() for kernel memory Thomas Gleixner
2017-12-16 21:24 ` [patch V149 13/50] x86/mm: Remove superfluous barriers Thomas Gleixner
2017-12-16 21:24 ` [patch V149 14/50] x86/mm: Clarify which functions are supposed to flush what Thomas Gleixner
2017-12-16 21:24 ` [patch V149 15/50] x86/mm: Move the CR3 construction functions to tlbflush.h Thomas Gleixner
2017-12-16 21:24 ` [patch V149 16/50] x86/mm: Remove hard-coded ASID limit checks Thomas Gleixner
2017-12-16 21:24 ` [patch V149 17/50] x86/mm: Put MMU to hardware ASID translation in one place Thomas Gleixner
2017-12-16 21:24 ` [patch V149 18/50] x86/mm: Create asm/invpcid.h Thomas Gleixner
2017-12-16 21:24 ` [patch V149 19/50] x86/cpufeatures: Add X86_BUG_CPU_INSECURE Thomas Gleixner
2017-12-16 21:24 ` [patch V149 20/50] x86/mm/pti: Disable global pages if PAGE_TABLE_ISOLATION=y Thomas Gleixner
2017-12-16 21:24 ` [patch V149 21/50] x86/mm/pti: Prepare the x86/entry assembly code for entry/exit CR3 switching Thomas Gleixner
2017-12-16 21:24 ` [patch V149 22/50] x86/mm/pti: Add infrastructure for page table isolation Thomas Gleixner
2017-12-16 21:24 ` [patch V149 23/50] x86/mm/pti: Add mapping helper functions Thomas Gleixner
2017-12-16 21:24 ` [patch V149 24/50] x86/mm/pti: Allow NX poison to be set in p4d/pgd Thomas Gleixner
2017-12-16 21:24 ` [patch V149 25/50] x86/mm/pti: Allocate a separate user PGD Thomas Gleixner
2017-12-16 21:24 ` [patch V149 26/50] x86/mm/pti: Populate " Thomas Gleixner
2017-12-16 21:24 ` [patch V149 27/50] x86/mm/pti: Add functions to clone kernel PMDs Thomas Gleixner
2017-12-16 21:24 ` [patch V149 28/50] x86/mm/pti: Force entry through trampoline when PTI active Thomas Gleixner
2017-12-16 21:24 ` [patch V149 29/50] x86/fixmap: Move the CPU entry area into a separate PMD Thomas Gleixner
2017-12-16 21:24 ` [patch V149 30/50] x86/mm/pti: Share cpu_entry_area PMDs Thomas Gleixner
2017-12-16 21:24 ` [patch V149 31/50] x86/entry: Align entry text section to PMD boundary Thomas Gleixner
2017-12-16 21:24 ` [patch V149 32/50] x86/mm/pti: Share entry text PMD Thomas Gleixner
2017-12-16 21:24 ` [patch V149 33/50] x86/mm/pti: Map ESPFIX into user space Thomas Gleixner
2017-12-16 21:24 ` [patch V149 34/50] x86/fixmap: Move IDT fixmap into the cpu_entry_area range Thomas Gleixner
2017-12-16 21:24 ` [patch V149 35/50] x86/fixmap: Add debugstore entries to cpu_entry_area Thomas Gleixner
2017-12-16 21:24 ` [patch V149 36/50] x86/events/intel/ds: Map debug buffers in fixmap Thomas Gleixner
2017-12-16 21:24 ` [patch V149 37/50] x86/mm/64: Make a full PGD-entry size hole in the memory map Thomas Gleixner
2017-12-17 11:07   ` Kirill A. Shutemov
2017-12-16 21:24 ` [patch V149 38/50] x86/pti: Put the LDT in its own PGD if PTI is on Thomas Gleixner
2017-12-17 11:09   ` Kirill A. Shutemov [this message]
2017-12-16 21:24 ` [patch V149 39/50] x86/pti: Map the vsyscall page if needed Thomas Gleixner
2017-12-16 21:24 ` [patch V149 40/50] x86/mm: Allow flushing for future ASID switches Thomas Gleixner
2017-12-16 21:24 ` [patch V149 41/50] x86/mm: Abstract switching CR3 Thomas Gleixner
2017-12-16 21:24 ` [patch V149 42/50] x86/mm: Use/Fix PCID to optimize user/kernel switches Thomas Gleixner
2017-12-16 21:24 ` [patch V149 43/50] x86/mm: Optimize RESTORE_CR3 Thomas Gleixner
2017-12-16 21:24 ` [patch V149 44/50] x86/mm: Use INVPCID for __native_flush_tlb_single() Thomas Gleixner
2017-12-16 21:24 ` [patch V149 45/50] x86/mm: Clarify the whole ASID/kernel PCID/user PCID naming Thomas Gleixner
2017-12-16 21:24 ` [patch V149 46/50] x86/mm/pti: Add Kconfig Thomas Gleixner
2017-12-16 21:24 ` [patch V149 47/50] x86/mm/dump_pagetables: Add page table directory Thomas Gleixner
2017-12-16 21:24 ` [patch V149 48/50] x86/mm/dump_pagetables: Check user space page table for WX pages Thomas Gleixner
2017-12-16 21:24 ` [patch V149 49/50] x86/mm/dump_pagetables: Allow dumping current pagetables Thomas Gleixner
2017-12-16 21:24 ` [patch V149 50/50] x86/ldt: Make the LDT mapping RO Thomas Gleixner

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