From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932645AbdLRLfx (ORCPT ); Mon, 18 Dec 2017 06:35:53 -0500 Received: from mail-wm0-f65.google.com ([74.125.82.65]:37672 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758438AbdLRLfv (ORCPT ); Mon, 18 Dec 2017 06:35:51 -0500 X-Google-Smtp-Source: ACJfBouzVdJtiaVsECO1ESpC1jytM+gkatepDzSS3fPNwD7koja1ewPkK89GPoXwLFf9MSMijqBMhw== From: Jerome Brunet To: Kevin Hilman , Carlo Caione Cc: Jerome Brunet , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] ARM64: meson-axg: enable hardware rng Date: Mon, 18 Dec 2017 12:35:46 +0100 Message-Id: <20171218113546.13116-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable the hardware random generator Signed-off-by: Jerome Brunet --- Hi Kevin, This patch depends on the changes adding the ethernet controller [0], for including the axg clock binding header. Cheers Jerome [0]: https://lkml.kernel.org/r/20171216035527.96952-2-yixun.lan@amlogic.com arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index dea1bc31b4de..c741fc16486f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -212,6 +212,13 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; + hwrng: rng { + compatible = "amlogic,meson-rng"; + reg = <0x0 0x18 0x0 0x4>; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; + }; + pinctrl_periphs: pinctrl@480 { compatible = "amlogic,meson-axg-periphs-pinctrl"; #address-cells = <2>; -- 2.14.3