From: Ingo Molnar <mingo@kernel.org>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Dave Hansen <dave.hansen@intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
LKML <linux-kernel@vger.kernel.org>,
x86@kernel.org, Linus Torvalds <torvalds@linux-foundation.org>,
Andy Lutomirsky <luto@kernel.org>,
Borislav Petkov <bpetkov@suse.de>,
Greg KH <gregkh@linuxfoundation.org>,
keescook@google.com, hughd@google.com,
Brian Gerst <brgerst@gmail.com>,
Josh Poimboeuf <jpoimboe@redhat.com>,
Denys Vlasenko <dvlasenk@redhat.com>,
Rik van Riel <riel@redhat.com>,
Boris Ostrovsky <boris.ostrovsky@oracle.com>,
Juergen Gross <jgross@suse.com>,
David Laight <David.Laight@aculab.com>,
Eduardo Valentin <eduval@amazon.com>,
aliguori@amazon.com, Will Deacon <will.deacon@arm.com>,
daniel.gruss@iaik.tugraz.at,
Dave Hansen <dave.hansen@linux.intel.com>,
Borislav Petkov <bp@suse.de>, "H. Peter Anvin" <hpa@zytor.com>
Subject: Re: [patch V163 27/51] x86/mm/pti: Populate user PGD
Date: Tue, 19 Dec 2017 08:48:35 +0100 [thread overview]
Message-ID: <20171219074835.3yc56k3z7adzlf6a@gmail.com> (raw)
In-Reply-To: <20171218205732.ql7ejvd743hceotf@hirez.programming.kicks-ass.net>
* Peter Zijlstra <peterz@infradead.org> wrote:
> On Mon, Dec 18, 2017 at 12:45:13PM -0800, Dave Hansen wrote:
> > On 12/18/2017 12:41 PM, Peter Zijlstra wrote:
> > >> I also don't think the user_shared area of the fixmap can get *that*
> > >> big. Does anybody know offhand what the theoretical limits are there?
> > > Problem there is the nr_cpus term I think, we currently have up to 8k
> > > CPUs, but I can see that getting bigger in the future.
> >
> > It only matters if we go over 512GB, though. Is the per-cpu part of the
> > fixmap ever more than 512GB/8k=64MB?
>
> Unlikely, I think the LDT (@ 32 pages / 128K) and the DS (@ 2*4 pages /
> 32K) are the largest entries in there.
Note that with the latest state of things the LDT is not in the fixmap anymore,
it's mapped separately, via Andy's following patch:
e86aaee3f2d9: ("x86/pti: Put the LDT in its own PGD if PTI is on")
We have the IDT, the per-CPU entry area and the Debug Store (on Intel CPUs) mapped
in the fixmap area, in addition to the usual fixmap entries that are a handful of
pages. (That's on 64-bit - on 32-bit we have a pretty large kmap area.)
The biggest contribution to the size of the fixmap area is struct cpu_entry_area
(FIX_CPU_ENTRY_AREA_BOTTOM..FIX_CPU_ENTRY_AREA_TOP), which is ~180k, i.e. 44
pages.
Our current NR_CPUS limit is 8,192 CPUs, but even with 65,536 CPUs the fixmap area
would still only be ~12 GB total - so we are far from running out of space.
Btw., the DS portion of the fixmap is not 64K but 128K. Here's the current size
distribution of struct cpu_entry_area:
::gdt - 4K
::tss - 12K
::entry_trampoline - 4K
#if 64-bit
::exception_stacks - 20K
#endif
#if Intel
::cpu_debug_store - 4K
::cpu_debug_buffers - 128K
#endif
So ::cpu_debug_buffers (struct debug_store_buffers) is the biggest fixmap chunk,
by far, distributed the following way:
::bts_buffer[] - 64K
::pebs_buffer[] - 64K
Thanks,
Ingo
next prev parent reply other threads:[~2017-12-19 7:48 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-18 11:42 [patch V163 00/51] x86/pti: Updated patch queue Thomas Gleixner
2017-12-18 11:42 ` [patch V163 01/51] x86/mm/dump_pagetables: Check PAGE_PRESENT for real Thomas Gleixner
2017-12-18 14:07 ` Borislav Petkov
2017-12-18 11:42 ` [patch V163 02/51] x86/vsyscall/64: Explicitly set _PAGE_USER in the pagetable hierarchy Thomas Gleixner
2017-12-18 14:21 ` Borislav Petkov
2017-12-18 11:42 ` [patch V163 03/51] x86/vsyscall/64: Warn and fail vsyscall emulation in NATIVE mode Thomas Gleixner
2017-12-18 14:44 ` Borislav Petkov
2017-12-18 11:42 ` [patch V163 04/51] arch: Allow arch_dup_mmap() to fail Thomas Gleixner
2017-12-18 11:42 ` [patch V163 05/51] x86/ldt: Rework locking Thomas Gleixner
2017-12-18 11:42 ` [patch V163 06/51] x86/ldt: Prevent ldt inheritance on exec Thomas Gleixner
2017-12-18 11:42 ` [patch V163 07/51] x86/mm/64: Improve the memory map documentation Thomas Gleixner
2017-12-18 11:42 ` [patch V163 08/51] x86/doc: Remove obvious weirdness Thomas Gleixner
2017-12-18 11:42 ` [patch V163 09/51] x86/entry: Remove SYSENTER_stack naming Thomas Gleixner
2017-12-18 11:42 ` [patch V163 10/51] x86/uv: Use the right tlbflush API Thomas Gleixner
2017-12-18 11:42 ` [patch V163 11/51] x86/microcode: Dont abuse the tlbflush interface Thomas Gleixner
2017-12-18 11:42 ` [patch V163 12/51] x86/mm: Use __flush_tlb_one() for kernel memory Thomas Gleixner
2017-12-18 11:42 ` [patch V163 13/51] x86/mm: Remove superfluous barriers Thomas Gleixner
2017-12-18 11:42 ` [patch V163 14/51] x86/mm: Clarify which functions are supposed to flush what Thomas Gleixner
2017-12-18 11:42 ` [patch V163 15/51] x86/mm: Move the CR3 construction functions to tlbflush.h Thomas Gleixner
2017-12-18 11:42 ` [patch V163 16/51] x86/mm: Remove hard-coded ASID limit checks Thomas Gleixner
2017-12-18 11:42 ` [patch V163 17/51] x86/mm: Put MMU to hardware ASID translation in one place Thomas Gleixner
2017-12-18 11:42 ` [patch V163 18/51] x86/mm: Create asm/invpcid.h Thomas Gleixner
2017-12-18 11:42 ` [patch V163 19/51] init: Invoke init_espfix_bsp() from mm_init() Thomas Gleixner
2017-12-18 11:42 ` [patch V163 20/51] x86/cpufeatures: Add X86_BUG_CPU_INSECURE Thomas Gleixner
2017-12-18 11:42 ` [patch V163 21/51] x86/mm/pti: Disable global pages if PAGE_TABLE_ISOLATION=y Thomas Gleixner
2017-12-18 11:42 ` [patch V163 22/51] x86/mm/pti: Prepare the x86/entry assembly code for entry/exit CR3 switching Thomas Gleixner
2017-12-18 11:42 ` [patch V163 23/51] x86/mm/pti: Add infrastructure for page table isolation Thomas Gleixner
2017-12-18 11:42 ` [patch V163 24/51] x86/mm/pti: Add mapping helper functions Thomas Gleixner
2017-12-18 12:52 ` Peter Zijlstra
2017-12-18 11:42 ` [patch V163 25/51] x86/mm/pti: Allow NX poison to be set in p4d/pgd Thomas Gleixner
2017-12-18 11:42 ` [patch V163 26/51] x86/mm/pti: Allocate a separate user PGD Thomas Gleixner
2017-12-18 11:42 ` [patch V163 27/51] x86/mm/pti: Populate " Thomas Gleixner
2017-12-18 20:34 ` Dave Hansen
2017-12-18 20:41 ` Peter Zijlstra
2017-12-18 20:45 ` Dave Hansen
2017-12-18 20:57 ` Peter Zijlstra
2017-12-19 7:48 ` Ingo Molnar [this message]
2017-12-19 18:08 ` Thomas Gleixner
2017-12-20 0:22 ` Thomas Gleixner
2017-12-20 16:26 ` Juergen Gross
2017-12-20 19:50 ` Thomas Gleixner
2017-12-18 22:11 ` Andy Lutomirski
2017-12-18 11:42 ` [patch V163 28/51] x86/mm/pti: Add functions to clone kernel PMDs Thomas Gleixner
2017-12-18 13:08 ` Peter Zijlstra
2017-12-18 11:42 ` [patch V163 29/51] x86/mm/pti: Force entry through trampoline when PTI active Thomas Gleixner
2017-12-18 11:42 ` [patch V163 30/51] x86/fixmap: Move the CPU entry area into a separate PMD Thomas Gleixner
2017-12-18 11:42 ` [patch V163 31/51] x86/mm/pti: Share cpu_entry_area PMDs Thomas Gleixner
2017-12-18 11:42 ` [patch V163 32/51] x86/entry: Align entry text section to PMD boundary Thomas Gleixner
2017-12-18 11:42 ` [patch V163 33/51] x86/mm/pti: Share entry text PMD Thomas Gleixner
2017-12-18 11:42 ` [patch V163 34/51] x86/mm/pti: Map ESPFIX into user space Thomas Gleixner
2017-12-18 11:42 ` [patch V163 35/51] x86/fixmap: Move IDT fixmap into the cpu_entry_area range Thomas Gleixner
2017-12-18 11:42 ` [patch V163 36/51] x86/fixmap: Add debugstore entries to cpu_entry_area Thomas Gleixner
2017-12-18 11:42 ` [patch V163 37/51] x86/events/intel/ds: Map debug buffers in fixmap Thomas Gleixner
2017-12-18 13:18 ` Peter Zijlstra
2017-12-18 11:42 ` [patch V163 38/51] x86/mm/64: Make a full PGD-entry size hole in the memory map Thomas Gleixner
2017-12-18 13:27 ` Peter Zijlstra
2017-12-19 18:09 ` Thomas Gleixner
2017-12-19 18:14 ` Thomas Gleixner
2017-12-18 11:42 ` [patch V163 39/51] x86/pti: Put the LDT in its own PGD if PTI is on Thomas Gleixner
2017-12-18 13:46 ` Peter Zijlstra
2017-12-18 11:42 ` [patch V163 40/51] x86/pti: Map the vsyscall page if needed Thomas Gleixner
2017-12-18 11:42 ` [patch V163 41/51] x86/mm: Allow flushing for future ASID switches Thomas Gleixner
2017-12-18 11:42 ` [patch V163 42/51] x86/mm: Abstract switching CR3 Thomas Gleixner
2017-12-18 11:42 ` [patch V163 43/51] x86/mm: Use/Fix PCID to optimize user/kernel switches Thomas Gleixner
2017-12-18 11:42 ` [patch V163 44/51] x86/mm: Optimize RESTORE_CR3 Thomas Gleixner
2017-12-18 11:43 ` [patch V163 45/51] x86/mm: Use INVPCID for __native_flush_tlb_single() Thomas Gleixner
2017-12-18 11:43 ` [patch V163 46/51] x86/mm: Clarify the whole ASID/kernel PCID/user PCID naming Thomas Gleixner
2017-12-18 11:43 ` [patch V163 47/51] x86/mm/pti: Add Kconfig Thomas Gleixner
2017-12-18 11:43 ` [patch V163 48/51] x86/mm/dump_pagetables: Add page table directory Thomas Gleixner
2017-12-18 11:43 ` [patch V163 49/51] x86/mm/dump_pagetables: Check user space page table for WX pages Thomas Gleixner
2017-12-18 11:43 ` [patch V163 50/51] x86/mm/dump_pagetables: Allow dumping current pagetables Thomas Gleixner
2017-12-18 11:43 ` [patch V163 51/51] x86/ldt: Make the LDT mapping RO Thomas Gleixner
2017-12-18 13:48 ` Peter Zijlstra
2017-12-18 12:11 ` [patch V163 00/51] x86/pti: Updated patch queue Ingo Molnar
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