From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966916AbdLSJck (ORCPT ); Tue, 19 Dec 2017 04:32:40 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:15660 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932971AbdLSJc2 (ORCPT ); Tue, 19 Dec 2017 04:32:28 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , Mark Rutland , Russell King , , , , , , , Subject: [PATCH 1/7] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode Date: Tue, 19 Dec 2017 15:01:27 +0530 Message-ID: <20171219093133.16565-2-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171219093133.16565-1-kishon@ti.com> References: <20171219093133.16565-1-kishon@ti.com> MIME-Version: 1.0 Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable PCIe x2 lane mode are added here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ac9216293b7c..9966d82dbd7c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -309,6 +309,8 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -334,6 +336,8 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; }; -- 2.11.0