From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752940AbdLSQCM (ORCPT ); Tue, 19 Dec 2017 11:02:12 -0500 Received: from bombadil.infradead.org ([65.50.211.133]:35279 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751297AbdLSQCI (ORCPT ); Tue, 19 Dec 2017 11:02:08 -0500 Date: Tue, 19 Dec 2017 17:01:55 +0100 From: Peter Zijlstra To: Zhang Rui Cc: Thomas Gleixner , LKML , linux-x86 , Len Brown , "Chen, Yu C" Subject: Re: Regression: unable to boot after commit bd9240a18edf ("x86/apic: Add TSC_DEADLINE quirk due to errata") - Surface Pro 4 SKL Message-ID: <20171219160155.zgu5clv5mj2l4aaj@hirez.programming.kicks-ass.net> References: <20171128081440.mi3nrhxgori75cbs@hirez.programming.kicks-ass.net> <1511857335.2498.22.camel@intel.com> <1511866741.2441.5.camel@intel.com> <20171128123607.fmgpq76brf6bdkk4@hirez.programming.kicks-ass.net> <1511966690.2750.9.camel@intel.com> <20171218202822.juwyxsd7millme7o@hirez.programming.kicks-ass.net> <1513680504.2569.1.camel@intel.com> <20171219152307.ugmlynst574wsdne@hirez.programming.kicks-ass.net> <1513698161.2745.14.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1513698161.2745.14.camel@intel.com> User-Agent: NeoMutt/20170609 (1.8.3) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Dec 19, 2017 at 11:42:41PM +0800, Zhang Rui wrote: > On Tue, 2017-12-19 at 16:23 +0100, Peter Zijlstra wrote: > > [    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) > > [    0.000000] ACPI: IRQ0 used by override. > > > > So your ACPI table has an override for IRQ2 and routes it to IRQ0. ^ this > > The HPET document says: > > > >   If the ENABLE_CNF bit and the LEG_RT_CNF bit are both set, then the > >   interrupts will be routed as follows: > > > >     Timer 0 will be routed to IRQ0 in Non-APIC or IRQ2 in the I/O APIC > > But AFAICS, the HPET emulated timer interrupts goes to IRQ0 Right, so see that ACPI override, that routes I/O APIC IRQ2 to IRQ0, or it _should_. Clearly something is messed up here.. but I've no idea what. That whole IRQ routing stuff is confusing.